Patents by Inventor Kosuke Kitaichi

Kosuke Kitaichi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240170346
    Abstract: In a wafer test step, a dummy semiconductor element formed in a scribe region of a semiconductor substrate is inspected by using a testing electrode provided in the scribe region and electrically connected to the dummy semiconductor element. In a dicing step, the scribe region of the semiconductor substrate is cut by using a dicing blade. The testing electrode includes a plurality of pad portions and a plurality of connection portions connecting the plurality of pad portions to each other. A width of each of the plurality of connection portions is larger than a width of the dicing blade, and smaller than a width of each of the plurality of pad portions. In plan view, the plurality of pad portions is arranged in a linear manner in a moving direction of the dicing blade, and the plurality of connection portions is arranged in a staggered manner in the moving direction.
    Type: Application
    Filed: August 21, 2023
    Publication date: May 23, 2024
    Inventor: Kosuke KITAICHI
  • Publication number: 20240063059
    Abstract: In a case where a crack occurs in a dicing step, the crack can be suppressed from proceeding toward an element region. A first scribe region and a second scribe region that both define an element region are formed in a main surface of a semiconductor wafer. In the first scribe region, an evaluation-deep-trench group including an evaluation-deep-trench-first portion and an evaluation-deep-trench-second portion is formed. The evaluation-deep-trench-first portion is formed in a first region. The evaluation-deep-trench-second portion has a width in an X-axis direction, and is formed in a bar shape extending in a Y-axis direction, in a second region located between the first region and the element region.
    Type: Application
    Filed: May 3, 2023
    Publication date: February 22, 2024
    Inventors: Koichi ANDO, Toshiyuki HATA, Kosuke KITAICHI, Hiroi OKA
  • Publication number: 20230378032
    Abstract: To manufacture a semiconductor device, a first heat treatment for curing a first adhesive material of a conductive paste type is performed, after a semiconductor chip is mounted on a die pad of a lead frame via the first adhesive material. After that, a metal plate is disposed on a pad of the semiconductor chip such that the metal plate faces the pad of the semiconductor chip via a second adhesive material of a conductive paste type, and a second heat treatment is performed for curing each of the first adhesive material and the second adhesive material. A time of the first heat treatment is less than a time of the second heat treatment. After the first adhesive material is cured by the first heat treatment, the first adhesive material is further cured by the second heat treatment.
    Type: Application
    Filed: February 28, 2023
    Publication date: November 23, 2023
    Inventors: Kosuke KITAICHI, Masatoshi SUGIURA, Hideaki TAMIMOTO, Takehiko MAEDA, Keita TAKADA, Yoshitaka KYOUGOKU
  • Patent number: 8378459
    Abstract: In a state where an adhesive tape is attached onto a main surface of a semiconductor wafer, a trench is formed in a rear surface of the semiconductor wafer. For forming the trench in the rear surface of the semiconductor wafer, after coating a resist film on the rear surface of the semiconductor wafer, the resist film is patterned by using the photolithography technology. The patterning of the resist film is performed so as not to leave the resist film in the region where the trench is to be formed. Then, the trench is formed in a predetermined region of the semiconductor wafer by the dry etching technology using the patterned resist film as a mask. Specifically, the trench is formed in the region near the dicing line.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: February 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Naka, Naotaka Tanaka, Toshihide Uematsu, Chuichi Miyazaki, Kazunari Suzuki, Yasuyuki Nakajima, Yoshiyuki Abe, Kenji Kohzu, Kosuke Kitaichi, Shinya Ogane
  • Publication number: 20100308442
    Abstract: In a state where an adhesive tape is attached onto a main surface of a semiconductor wafer, a trench is formed in a rear surface of the semiconductor wafer. For forming the trench in the rear surface of the semiconductor wafer, after coating a resist film on the rear surface of the semiconductor wafer, the resist film is patterned by using the photolithography technology. The patterning of the resist film is performed so as not to leave the resist film in the region where the trench is to be formed. Then, the trench is formed in a predetermined region of the semiconductor wafer by the dry etching technology using the patterned resist film as a mask. Specifically, the trench is formed in the region near the dicing line.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 9, 2010
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuhiro NAKA, Naotaka TANAKA, Toshihide UEMATSU, Chuichi MIYAZAKI, Kazunari SUZUKI, Yasuyuki NAKAJIMA, Yoshiyuki ABE, Kenji KOHZU, Kosuke KITAICHI, Shinya OGANE