Abstract: To improve a reading speed and a writing speed while preventing occurrence of disturbance in a resistance storage element, specifically, a nonvolatile storage device that has a memory having at least one nonvolatile resistance storage element and a control unit configured to write a high resistance state or a low resistance state to the resistance storage element, wherein the control unit applies a bias to the resistance storage element in a verification operation carried out after writing the high resistance state, or applies a bias to the resistance storage element in a verification operation carried out after writing the low resistance state, these biases being in directions opposite to each other.

Abstract: To reduce deterioration of non-volatile memory and write data at higher speed, writing data is stored in a ReRAM when a page utilization rate R is lower than a threshold Rth1 and/or the writing data is frequently-rewritten data. With an empty space Semp2 in the ReRAM being less than a threshold Sth (step S110), when the data in the ReRAM is infrequently-rewritten data and the page utilization rate R obtained if target data is stored in a flash memory 22 is equal to or higher than a threshold value Rth3 (steps S120 and S130), data of logical sectors contained in N logical page addresses stored in a transfer list is read from the ReRAM to be written to the flash memory (steps S140 to S160). These steps reduce deterioration of the flash memory and allow higher data writing.

Abstract: Degradation in processing capability due to copying during garbage collection is reduced. A data storage system includes a memory unit provided with a memory, into which data are written in units of pages, and a memory controller that controls writing of data to the memory; and a controller that indicates, to the memory controller, a logical page address to which data are to be written. The memory controller determines a target block that is a block to be erased when garbage collection is next performed and provides the controller with information on a logical page address corresponding to a physical page address of a valid page in the target block. The controller instructs the memory controller to write data to the logical page address received from the memory controller.

Abstract: To improve a reading speed and a writing speed while preventing occurrence of disturbance in a resistance storage element, specifically, a nonvolatile storage device that has a memory having at least one nonvolatile resistance storage element and a control unit configured to write a high resistance state or a low resistance state to the resistance storage element, wherein the control unit applies a bias to the resistance storage element in a verification operation carried out after writing the high resistance state, or applies a bias to the resistance storage element in a verification operation carried out after writing the low resistance state, these biases being in directions opposite to each other.

Abstract: To improve a reading speed and a writing speed while preventing occurrence of disturbance in a resistance storage element, specifically, a nonvolatile storage device includes a memory including at least one nonvolatile resistance storage element and a control unit configured to write a high resistance state or a low resistance state to the resistance storage element, wherein the control unit applies a bias to the resistance storage element in a verification operation carried out after writing the high resistance state, or applies a bias to the resistance storage element in a verification operation carried out after writing the low resistance state, these biases being in directions opposite to each other. An object of the present invention is to improve a reading speed and a writing speed while preventing occurrence of disturbance in a resistance storage element.

Abstract: To reduce deterioration of non-volatile memory and write data at higher speed, writing data is stored in a ReRAM when a page utilization rate R is lower than a threshold Rth1 and/or the writing data is frequently-rewritten data. With an empty space Semp2 in the ReRAM being less than a threshold Sth (step S110), when the data in the ReRAM is infrequently-rewritten data and the page utilization rate R obtained if target data is stored in a flash memory 22 is equal to or higher than a threshold value Rth3 (steps S120 and S130), data of logical sectors contained in N logical page addresses stored in a transfer list is read from the ReRAM to be written to the flash memory (steps S140 to S160). These steps reduce deterioration of the flash memory and allow higher data writing.

Abstract: Voltages are applied to supply voltage application points of memory cells of an SRAM, a semiconductor substrate, a word line and bit lines so that voltage Vdd takes value V1, substrate voltage Vsub becomes 0 V, word line voltage Vw1 takes value V1, bit line voltage Vbll becomes 0 V, and bit line voltage Vblr takes value V1, the voltage difference between the word line and one of the bit lines is forced to be equal to a voltage difference V1h higher than a normal voltage difference V1 and the voltage difference between the word line and the other bit line is forced to be equal the normal voltage difference V1 lower than the voltage V1h to inject electrons into an insulating layer near a diffusion layer connected to an output terminal of an inverter constituting the memory cell. This can improve the operating characteristics of the memory cell.