Patents by Inventor Kosuke Nishihara

Kosuke Nishihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200234186
    Abstract: A classification apparatus includes: an encoding module that includes an element classification part that extracts a feature of input data and outputs classification information based on an element classification model stored in a first storage unit; an integration module that includes an element estimation part that receives the classification information and converts the classification information to a collation vector based on an element estimation model stored in a second storage unit; and a determination module that includes a determination part that determines a group to which the collation vector belongs by collating the collation vector with a representative vector of an individual group stored as a semantic model in a third storage unit and outputs a group ID of the group as a classification result.
    Type: Application
    Filed: February 20, 2018
    Publication date: July 23, 2020
    Applicant: NEC Corporation
    Inventors: Kosuke NISHIHARA, Norihiko TAYA
  • Publication number: 20180164765
    Abstract: A service control device includes a controller that receives one of an external request and an execution result of a functional element and directs a functional element to be carried out next by referring to a control list holding a plan of combination of functional elements; an execution unit configured to carry out the functional element directed by the controller; a monitoring and recording unit configured to monitor an execution state of a functional element and record; and an activation level calculating unit configured to calculate an activation level of a functional element based on the execution state of a functional element having been recorded and update the control list based on the activation level.
    Type: Application
    Filed: June 10, 2016
    Publication date: June 14, 2018
    Applicant: NEC CORPORATION
    Inventor: Kosuke NISHIHARA
  • Publication number: 20170262044
    Abstract: An information processing apparatus according to the present invention includes: a detection unit that detects detection information that is information indicating an external state of the apparatus; a communication unit that receives reception information that is a determination result given by another apparatus; and a control unit that calculates a first determination result that is a result acquired by determining a state of a surrounding of the apparatus based on the detection information and the reception information, transmits the first determination result to the another apparatus via the communication unit, and activates a necessary function for the detection unit or the communication unit and stops an unnecessary function thereof.
    Type: Application
    Filed: September 7, 2015
    Publication date: September 14, 2017
    Applicant: NEC Corporation
    Inventors: Takashi TAKENAKA, Shuichi TAHARA, Kenichi OYAMA, Nobuharu KAMI, Hiroto SUGAHARA, Noboru SAKIMURA, Kosuke NISHIHARA, Naoki KASAI
  • Patent number: 8938740
    Abstract: A parameter determination unit 110 substitutes, for each of a plurality of applications, a recommended amount of resources and a quality of experience corresponding to the recommended amount of resources, and a minimum amount of resources and a quality of experience corresponding to the minimum amount of resources into a quality function f in expression (1) indicating a relation between an amount of resources R and a quality of experience Q, to determine parameters a and b. A resource amount determination unit 120 determines an amount of resources to be allocated to the plurality of applications using the quality function f for each application in which the parameters a and b are determined. The quality function f(x) is a monotonically increasing function having an inverse function f?1, connects (??,0) and (+?,1), and is symmetrical with respect to x=0.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: January 20, 2015
    Assignee: NEC Corporation
    Inventors: Kosuke Nishihara, Kazuhisa Ishizaka
  • Patent number: 8897372
    Abstract: To reduce performance degradation due to a high-performance core's waiting for a processing result of a low-performance core in a multi-core processor including a plurality of cores with different running performance, included are a task pool that stores executable tasks for each computational core, a task scheduler, and a reference count analysis module that acquires hint information and a reference count estimation method from a running task and estimates a reference count of a task to be newly inserted into the task pool or a task existing in the task pool based on the specified method. The scheduler performs insertion and acquisition of a task by mainly using performance of the cores and the reference count.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: November 25, 2014
    Assignee: NEC Corporation
    Inventors: Kosuke Nishihara, Kazuhisa Ishizaka
  • Patent number: 8635405
    Abstract: In a multi-core processor system, cache memories are provided respectively for a plurality of processors. An assignment management unit manages assignment of tasks to the processors. A cache status calculation unit calculates a cache usage status such as a memory access count and a cache hit ratio, with respect to each task. A first processor handles a plurality of first tasks that belong to a first process. If computation amount of the first process exceeds a predetermined threshold value, the assignment management unit refers to the cache usage status to preferentially select, as a migration target task, one of the plurality of first tasks whose memory access count is smaller or whose cache hit ratio is higher. Then, the assignment management unit newly assigns the migration target task to a second processor handling another process different from the first processor.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: January 21, 2014
    Assignee: NEC Corporation
    Inventors: Kosuke Nishihara, Kazuhisa Ishizaka
  • Patent number: 8555291
    Abstract: Provided are a synchronization control section that executes a current thread and a reference thread in parallel, a waiting time calculation section that calculates the time needed for the reference thread to reach a second synchronization point as a waiting time of the current thread when the reference thread does not reach the second synchronization point at a time when the current thread reaches a first synchronization point, a quality difference calculation section that estimates a quality difference between data that the current thread generates by referring to processing data at the second synchronization point of the reference thread and data that the current thread generates without referring to the processing data, and a synchronization determination section that determines whether to make the current thread wait until the reference thread reaches the second synchronization point depending on the waiting time and the magnitude of the quality difference.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: October 8, 2013
    Assignee: NEC Corporation
    Inventor: Kosuke Nishihara
  • Patent number: 8533726
    Abstract: Provided is a computing resource allocation device capable of allocating computing resources to accommodate changing activity patterns. The device is equipped with an external environment recognition means that analyzes input values from sensors to specify the current environment, a memory means that stores a table in which the sensors required to specify the environment are correlated, a transition frequency computation means that computes the transition frequency at which a transition is made from an environment to another environment, and a computing resource allocation means that computes the amount of allocation of the computing resources to be used for the analysis based on the current environment by referencing the table and the transition frequency, and that allocates the computing resources for the analysis.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: September 10, 2013
    Assignee: NEC Corporation
    Inventors: Kosuke Nishihara, Kazuhisa Ishizaka
  • Patent number: 8446951
    Abstract: To provide a dynamic image receiving apparatus which receives dynamic image streams coded with inter-frame prediction such as MPEG from a plurality of channels, and collects the dynamic image streams containing intra-frame coded pictures from each channel in a short time. The dynamic image receiving apparatus includes: a time information accumulative processing device which accumulates code receiving time of the intra-frame coded picture of the dynamic image stream, and periodicity time information containing one of or both of presentation time information and decoding time information contained in the dynamic image stream for each dynamic image stream of the plurality of channels; code receiving time predicting devices which predict the code receiving time of the intra-frame coded pictures based on the periodicity time information; and a channel selection control device which controls channel selection of the dynamic image stream to be received based on the predicted code receiving time information.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: May 21, 2013
    Assignee: NEC Corporation
    Inventors: Katsunori Tanaka, Atsushi Hatabu, Yuzo Senda, Katsutoshi Seki, Tomoyoshi Kobori, Kosuke Nishihara, Soji Mori
  • Patent number: 8447933
    Abstract: In a multi-core processor of a shared-memory type, deterioration in the data processing capability caused by competitions of memory accesses from a plurality of processors is suppressed effectively. In a memory access controlling system for controlling accesses to a cache memory in a data read-ahead process when the multi-core processor of a shared-memory type performs a task including a data read-ahead thread for executing data read-ahead and a parallel execution thread for performing an execution process in parallel with the data read-ahead, the system includes a data read-ahead controller which controls an interval between data read-ahead processes in the data read-ahead thread adaptive to a data flow which varies corresponding to an input value of the parallel process in the parallel execution thread. By controlling the interval between the data read-ahead processes, competitions of memory accesses in the multi-core processor are suppressed.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: May 21, 2013
    Assignee: NEC Corporation
    Inventor: Kosuke Nishihara
  • Publication number: 20120324469
    Abstract: A parameter determination unit 110 substitutes, for each of a plurality of applications, a recommended amount of resources and a quality of experience corresponding to the recommended amount of resources, and a minimum amount of resources and a quality of experience corresponding to the minimum amount of resources into a quality function fin expression (1) indicating a relation between an amount of resources R and a quality of experience Q, to determine parameters a and b. A resource amount determination unit 120 determines an amount of resources to be allocated to the plurality of applications using the quality function f for each application in which the parameters a and b are determined. The quality function f(x) is a monotonically increasing function having an inverse function f?1, connects (??) and (+?), and is symmetrical with respect to x=0. Q=f(x)=f((R?a)/b) ??(1).
    Type: Application
    Filed: December 9, 2010
    Publication date: December 20, 2012
    Applicant: NEC CORPORATION
    Inventors: Kosuke Nishihara, Kazuhisa Ishizaka
  • Publication number: 20110310977
    Abstract: To reduce performance degradation due to a high-performance core's waiting for a processing result of a low-performance core in a multi-core processor including a plurality of cores with different running performance, included are a task pool that stores executable tasks for each computational core, a task scheduler, and a reference count analysis module that acquires hint information and a reference count estimation method from a running task and estimates a reference count of a task to be newly inserted into the task pool or a task existing in the task pool based on the specified method. The scheduler performs insertion and acquisition of a task by mainly using performance of the cores and the reference count.
    Type: Application
    Filed: January 22, 2010
    Publication date: December 22, 2011
    Inventors: Kosuke Nishihara, Kazuhisa Ishizaka
  • Publication number: 20110314225
    Abstract: In a multi-core processor system, cache memories are provided respectively for a plurality of processors. An assignment management unit manages assignment of tasks to the processors. A cache status calculation unit calculates a cache usage status such as a memory access count and a cache hit ratio, with respect to each task. A first processor handles a plurality of first tasks that belong to a first process. If computation amount of the first process exceeds a predetermined threshold value, the assignment management unit refers to the cache usage status to preferentially select, as a migration target task, one of the plurality of first tasks whose memory access count is smaller or whose cache hit ratio is higher. Then, the assignment management unit newly assigns the migration target task to a second processor handling another process different from the first processor.
    Type: Application
    Filed: February 12, 2010
    Publication date: December 22, 2011
    Inventors: Kosuke Nishihara, Kazuhisa Ishizaka
  • Publication number: 20110276980
    Abstract: Provided is a computing resource allocation device capable of allocating computing resources to accommodate changing activity patterns. The device is equipped with an external environment recognition means that analyzes input values from sensors to specify the current environment, a memory means that stores a table in which the sensors required to specify the environment are correlated, a transition frequency computation means that computes the transition frequency at which a transition is made from an environment to another environment, and a computing resource allocation means that computes the amount of allocation of the computing resources to be used for the analysis based on the current environment by referencing the table and the transition frequency, and that allocates the computing resources for the analysis.
    Type: Application
    Filed: February 16, 2010
    Publication date: November 10, 2011
    Applicant: NEC CORPORATION
    Inventors: Kosuke Nishihara, Kazuhisa Ishizaka
  • Publication number: 20110047556
    Abstract: Provided are a synchronization control section that executes a current thread and a reference thread in parallel, a waiting time calculation section that calculates the time needed for the reference thread to reach a second synchronization point as a waiting time of the current thread when the reference thread does not reach the second synchronization point at a time when the current thread reaches a first synchronization point, a quality difference calculation section that estimates a quality difference between data that the current thread generates by referring to processing data at the second synchronization point of the reference thread and data that the current thread generates without referring to the processing data, and a synchronization determination section that determines whether to make the current thread wait until the reference thread reaches the second synchronization point depending on the waiting time and the magnitude of the quality difference.
    Type: Application
    Filed: January 14, 2009
    Publication date: February 24, 2011
    Inventor: Kosuke Nishihara
  • Publication number: 20110002395
    Abstract: A deblocking filtering processor includes a first deblocking filtering section provided with a typical filter intensity calculation section and a typical filter section. The typical filter intensity calculation section selects a predetermined pixel line among a plurality of pixel lines crossing a block boundary as a typical pixel line for decoded image data of a moving image that are coded in units of blocks, and performs a filter intensity calculation to obtain a typical filter intensity on the basis of pixel values included in the typical pixel line. The typical filter section provides smoothing for pixel values included in the plurality of pixel lines on the basis of the typical filter intensity.
    Type: Application
    Filed: March 27, 2009
    Publication date: January 6, 2011
    Applicant: NEC CORPORATION
    Inventor: Kosuke Nishihara
  • Publication number: 20100246673
    Abstract: To provide a dynamic image receiving apparatus which receives dynamic image streams coded with inter-frame prediction such as MPEG from a plurality of channels, and collects the dynamic image streams containing intra-frame coded pictures from each channel in a short time. The dynamic image receiving apparatus includes: a time information accumulative processing device which accumulates code receiving time of the intra-frame coded picture of the dynamic image stream, and periodicity time information containing one of or both of presentation time information and decoding time information contained in the dynamic image stream for each dynamic image stream of the plurality of channels; code receiving time predicting devices which predict the code receiving time of the intra-frame coded pictures based on the periodicity time information; and a channel selection control device which controls channel selection of the dynamic image stream to be received based on the predicted code receiving time information.
    Type: Application
    Filed: September 19, 2008
    Publication date: September 30, 2010
    Applicant: NEC CORPORATION
    Inventors: Katsunori Tanaka, Atsushi Hatabu, Yuzo Senda, Katsutoshi SEKI, Tomoyoshi Kobori, Kosuke Nishihara, Soji Mori
  • Publication number: 20100223431
    Abstract: In a multi-core processor of a shared-memory type, deterioration in the data processing capability caused by competitions of memory accesses from a plurality of processors is suppressed effectively. In a memory access controlling system for controlling accesses to a cache memory in a data read-ahead process when the multi-core processor of a shared-memory type performs a task including a data read-ahead thread for executing data read-ahead and a parallel execution thread for performing an execution process in parallel with the data read-ahead, the system includes a data read-ahead controller which controls an interval between data read-ahead processes in the data read-ahead thread adaptive to a data flow which varies corresponding to an input value of the parallel process in the parallel execution thread. By controlling the interval between the data read-ahead processes, competitions of memory accesses in the multi-core processor are suppressed.
    Type: Application
    Filed: February 4, 2008
    Publication date: September 2, 2010
    Inventor: Kosuke Nishihara