Patents by Inventor Kosuke Ohshima
Kosuke Ohshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7573109Abstract: A semiconductor device having high withstand strength against destruction. The semiconductor device 1 includes guard buried regions 44b of second conductivity type concentrically provided on a resistance layer 15 of first conductivity type and base diffusion regions 17a are provided inside of the guard buried region 44b and base buried regions 44a of the second conductivity type are provided on the bottom surface of the base diffusion regions 17a. A distance between adjacent base buried regions 44a at the bottom of the same base diffusion region 17a is Wm1, a distance between adjacent base buried regions 44a at the bottom of the different base diffusion regions 17a is Wm2, and a distance between the guard buried regions 44b is WPE. A ratio of an impurity quantity Q1 of the first conductivity type and an impurity quantity Q2 of the second conductivity type included inside the widthwise center of the innermost guard buried region 44b is 0.90<Q2/Q1 when Wm1<WPE<Wm2.Type: GrantFiled: September 28, 2006Date of Patent: August 11, 2009Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Shinji Kunori, Hiroaki Shishido, Masato Mikawa, Kosuke Ohshima, Masahiro Kuriyama, Mizue Kitada
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Patent number: 7365391Abstract: A semiconductor device having high withstand voltage is provided. An active groove 22a includes a long and narrow main groove part 26 and a sub groove part 27 connected to a longitudinal side surface of the main groove part, and a buried region 24 of a second conductivity type whose height is lower than the bottom surface of the base diffusion region 32a of the second conductivity type is provided on the bottom surface of the main groove part 26. An active groove filling region 25 of the second conductivity type in contact with the base diffusion region 32a is provided in the sub groove part 27. The buried region 24 is contacted to the base diffusion region 32a through the active groove filling region 25. Since one gate groove 83 is formed by the part above the buried region 24 in one active groove 22a, the gate electrode plugs 48 are not separated, which allows the electrode pattern to be simplified.Type: GrantFiled: September 28, 2006Date of Patent: April 29, 2008Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Toru Kurosaki, Shinji Kunori, Mizue Kitada, Kosuke Ohshima, Hiroaki Shishido, Masato Mikawa
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Patent number: 7282764Abstract: A semiconductor device having high ruggedness is provided. The distance Wm2 between buried regions, positioned at the bottoms of different base diffusion regions and face each other, is set smaller than the distance Wm1 between buried regions positioned at the bottom of the same base diffusion region (Wm1>Wm2). An avalanche breakdown occurs under the bottom of the base diffusion region, and the avalanche current is not passed through a high resistance part immediately under the source diffusion region in the base diffusion region, thereby providing high withstand strength against destruction.Type: GrantFiled: July 6, 2006Date of Patent: October 16, 2007Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Shinji Kunori, Hiroaki Shishido, Masato Mikawa, Kosuke Ohshima, Masahiro Kuriyama, Mizue Kitada
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Patent number: 7208375Abstract: A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.Type: GrantFiled: October 19, 2004Date of Patent: April 24, 2007Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
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Publication number: 20070069323Abstract: A semiconductor device having high withstand strength against destruction. The semiconductor device 1 includes guard buried regions 44b of second conductivity type concentrically provided on a resistance layer 15 of first conductivity type and base diffusion regions 17a are provided inside of the guard buried region 44b and base buried regions 44a of the second conductivity type are provided on the bottom surface of the base diffusion regions 17a. A distance between adjacent base buried regions 44a at the bottom of the same base diffusion region 17a is Wm1, a distance between adjacent base buried regions 44a at the bottom of the different base diffusion regions 17a is Wm2, and a distance between the guard buried regions 44b is WPE. A ratio of an impurity quantity Q1 of the first conductivity type and an impurity quantity Q2 of the second conductivity type included inside the widthwise center of the innermost guard buried region 44b is 0.90<Q2/Q1 when Wm1<WPE<Wm2.Type: ApplicationFiled: September 28, 2006Publication date: March 29, 2007Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Shinji Kunori, Hiroaki Shishido, Masato Mikawa, Kosuke Ohshima, Masahiro Kuriyama, Mizue Kitada
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Patent number: 7196376Abstract: An active groove filled region 23a is kept at a portion of an active groove 22a connecting to an embedded region 24 positioned below a gate groove 83. The active groove filled region 23a connects to a source electrode film 58a so as to have the same electric potential as a source region 64. When a reverse bias is applied between a base region 32a and a conductive layer 12, a reverse bias is also applied between the embedded region 24 and the conductive layer 12; and therefore, depletion layers spread out together and a withstanding voltage is increased.Type: GrantFiled: April 4, 2005Date of Patent: March 27, 2007Assignee: Shindengen Electric Manufacturing Co., Ltd.,Inventors: Toru Kurosaki, Shinji Kunori, Mizue Kitada, Kosuke Ohshima, Hiroaki Shishido
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Publication number: 20070045776Abstract: A semiconductor device having high ruggedness is provided. The distance Wm2 between buried regions, positioned at the bottoms of different base diffusion regions and face each other, is set smaller than the distance Wm1 between buried regions positioned at the bottom of the same base diffusion region (Wm1>Wm2). An avalanche breakdown occurs under the bottom of the base diffusion region, and the avalanche current is not passed through a high resistance part immediately under the source diffusion region in the base diffusion region, thereby providing high withstand strength against destruction.Type: ApplicationFiled: July 6, 2006Publication date: March 1, 2007Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Shinji Kunori, Hiroaki Shishido, Masato Mikawa, Kosuke Ohshima, Masahiro Kuriyama, Mizue Kitada
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Publication number: 20070045726Abstract: A semiconductor device having high withstand voltage is provided. An active groove 22a includes a long and narrow main groove part 26 and a sub groove part 27 connected to a longitudinal side surface of the main groove part, and a buried region 24 of a second conductivity type whose height is lower than the bottom surface of the base diffusion region 32a of the second conductivity type is provided on the bottom surface of the main groove part 26. An active groove filling region 25 of the second conductivity type in contact with the base diffusion region 32a is provided in the sub groove part 27. The buried region 24 is contacted to the base diffusion region 32a through the active groove filling region 25. Since one gate groove 83 is formed by the part above the buried region 24 in one active groove 22a, the gate electrode plugs 48 are not separated, which allows the electrode pattern to be simplified.Type: ApplicationFiled: September 28, 2006Publication date: March 1, 2007Applicant: Shindengen Electric Manufacturing Co., Ltd.Inventors: Toru Kurosaki, Shinji Kunori, Mizue Kitada, Kosuke Ohshima, Hiroaki Shishido, Masato Mikawa
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Publication number: 20060063335Abstract: A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.Type: ApplicationFiled: October 19, 2004Publication date: March 23, 2006Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
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Publication number: 20050224848Abstract: An active groove filled region 23a is kept at a portion of an active groove 22a connecting to an embedded region 24 positioned below a gate groove 83. The active groove filled region 23a connects to a source electrode film 58a so as to have the same electric potential as a source region 64. When a reverse bias is applied between a base region 32a and a conductive layer 12, a reverse bias is also applied between the embedded region 24 and the conductive layer 12; and therefore, depletion layers spread out together and a withstanding voltage is increased.Type: ApplicationFiled: April 4, 2005Publication date: October 13, 2005Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Toru Kurosaki, Shinji Kunori, Mizue Kitada, Kosuke Ohshima, Hiroaki Shishido
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Patent number: 6906355Abstract: A semiconductor device having guard grooves uniformly filled with a semiconductor filler is provided. The four corners of a rectangular ring-shaped guard groove meet at right angles, and outer and inner auxiliary diffusion regions both rounded are connected to the four corners. Since the guard grooves do not have to be rounded, the plane orientation of a silicon single crystal exposed inside the guard grooves can be all {100}. Therefore, epitaxial growth in the guard grooves is uniformly carried out, and the grooves are filled with guard regions without defects.Type: GrantFiled: October 3, 2003Date of Patent: June 14, 2005Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
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Patent number: 6876034Abstract: A semiconductor device having grooves uniformly filled with semiconductor fillers is provided. Both ends of each of narrow active grooves are connected to an inner circumferential groove surrounding the active grooves. The growth speed of semiconductor fillers on both ends of the active grooves becomes equal to that at their central portions. As a result, a semiconductor device having the active grooves filled with the semiconductor fillers at a uniform height is obtained.Type: GrantFiled: June 27, 2003Date of Patent: April 5, 2005Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
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Patent number: 6841825Abstract: A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.Type: GrantFiled: June 2, 2003Date of Patent: January 11, 2005Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
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Publication number: 20040070002Abstract: A semiconductor device having guard grooves uniformly filled with a semiconductor filler is provided. The four corners of a rectangular ring-shaped guard groove meet at right angles, and outer and inner auxiliary diffusion regions both rounded are connected to the four corners. Since the guard grooves do not have to be rounded, the plane orientation of a silicon single crystal exposed inside the guard grooves can be all {100}. Therefore, epitaxial growth in the guard grooves is uniformly carried out, and the grooves are filled with guard regions without defects.Type: ApplicationFiled: October 3, 2003Publication date: April 15, 2004Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
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Publication number: 20040021195Abstract: A semiconductor device having grooves uniformly filled with semiconductor fillers is provided. Both ends of each of narrow active grooves are connected to an inner circumferential groove surrounding the active grooves. The growth speed of semiconductor fillers on both ends of the active grooves becomes equal to that at their central portions. As a result, a semiconductor device having the active grooves filled with the semiconductor fillers at a uniform height is obtained.Type: ApplicationFiled: June 27, 2003Publication date: February 5, 2004Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
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Publication number: 20030227051Abstract: A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.Type: ApplicationFiled: June 2, 2003Publication date: December 11, 2003Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima