Patents by Inventor Kosuke Oshima
Kosuke Oshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11853198Abstract: A program development assistance system includes an automatic execution process server that accepts a commit completion notification indicating that a source code has been registered, commit information that includes source code information and ticket information is acquired, a ticket identifier is extracted from the commit information, attribute information pertaining to a ticket is acquired on the basis of the extracted ticket identifier, information to be executed that corresponds to the source code to be processed by automatic execution is stored in an automatic execution queue, the sequence of to-be-executed information in the automatic execution queue is altered on the basis of the acquired attribute information pertaining to the ticket, the source code and a test case that are to be processed by automatic execution are acquired, and an automatic execution process is performed using the source code and the test case on the basis of the sequence of to-be-executed information.Type: GrantFiled: November 19, 2020Date of Patent: December 26, 2023Assignee: HITACHI, LTD.Inventors: Noboru Wakabayashi, Masumi Kawakami, Kosuke Oshima, Akihiro Hori, Ryosuke Yasuoka
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Patent number: 11823097Abstract: Provided is a test facility management system that can evaluate, in a software development process requiring use of test facilities, progress of a process caused by increasing or decreasing a count of the test facilities. The test facility management system can include: a project progress forecast unit that stores a process information database, a facility reservation information database, a process progress history information database, and facility count proposed change information, calculates facility usage remaining time period for the software development process based on process progress history information, specifies a time range during which facilities of the count of proposed change are available, and forecasts, based on the available time range, the progress of the software development process when work for the facility usage remaining time period is carried out by the facilities of the count of the proposed change; and a user interface that outputs the forecasted progress information.Type: GrantFiled: December 10, 2019Date of Patent: November 21, 2023Assignee: HITACHI, LTD.Inventors: Kosuke Oshima, Masumi Kawakami, Makoto Ichii, Akihiro Hori, Yasufumi Suzuki
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Publication number: 20230081100Abstract: A risk evaluation system includes a processor unit and a storage unit. In the risk evaluation system, the storage unit stores: demand information indicating a demand for software to be developed in a software development project that is a risk evaluation target; past demand information indicating a demand for software developed in a past software development project; and a source code change history in the past software development project, and the processor unit is configured to: calculate a similarity between the demand information and the past demand information; extract a change history of a source code corresponding to the past demand information based on the past demand information and the source code change history; and evaluate a risk in software development for realizing the demand information based on the similarity and the change history of the source code corresponding to the past demand information.Type: ApplicationFiled: January 19, 2021Publication date: March 16, 2023Inventors: Kosuke OSHIMA, Masumi KAWAKAMI, Kenji KITAGAWA, Makoto ICHII, Akihiro HORI, Yuhao WU
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Publication number: 20220327047Abstract: A program development assistance system includes an automatic execution process server that accepts a commit completion notification indicating that a source code has been registered, commit information that includes source code information and ticket information is acquired, a ticket identifier is extracted from the commit information, attribute information pertaining to a ticket is acquired on the basis of the extracted ticket identifier, information to be executed that corresponds to the source code to be processed by automatic execution is stored in an automatic execution queue, the sequence of to-be-executed information in the automatic execution queue is altered on the basis of the acquired attribute information pertaining to the ticket, the source code and a test case that are to be processed by automatic execution are acquired, and an automatic execution process is performed using the source code and the test case on the basis of the sequence of to-be-executed information.Type: ApplicationFiled: November 19, 2020Publication date: October 13, 2022Inventors: Noboru WAKABAYASHI, Masumi KAWAKAMI, Kosuke OSHIMA, Akihiro HORI, Ryosuke YASUOKA
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Publication number: 20220051148Abstract: Provided is a test facility management system that can evaluate, in a software development process requiring use of test facilities, progress of a process caused by increasing or decreasing a count of the test facilities. The test facility management system can include: a project progress forecast unit that stores a process information database, a facility reservation information database, a process progress history information database, and facility count proposed change information, calculates facility usage remaining time period for the software development process based on process progress history information, specifies a time range during which facilities of the count of proposed change are available, and forecasts, based on the available time range, the progress of the software development process when work for the facility usage remaining time period is carried out by the facilities of the count of the proposed change; and a user interface that outputs the forecasted progress information.Type: ApplicationFiled: December 10, 2019Publication date: February 17, 2022Applicant: Hitachi, Ltd.Inventors: Kosuke Oshima, Masumi Kawakami, Makoto Ichii, Akihiro Hori, Yasufumi Suzuki
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Patent number: 9804023Abstract: A glare measuring system is configured to have an imaging camera which is supported to be rotatable within a horizontal plane, and a processing device which calculates equivalent veiling luminance on the basis of a pickup image of the imaging camera and calculates the value of a glare rating GR on the basis of the equivalent veiling luminance. The imaging camera has a super-wide-angle lens mounted thereon, and picks up an image in a position which is rotated within the horizontal plane by every angle corresponding to the angle of view ? of the super-wide-angle. The processing device combines pickup images to generate a composite image in which a glare measurement direction is set to the center of the composite image, calculates equivalent veiling luminance on the basis of the composite image, and calculates the value of the glare rating in the glare measurement direction.Type: GrantFiled: February 25, 2013Date of Patent: October 31, 2017Assignee: IWASAKI ELECTRIC CO., LTD.Inventors: Tetsuji Yamada, Kosuke Oshima
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Publication number: 20150035972Abstract: A glare measuring system is configured to have an imaging camera which is supported to be rotatable within a horizontal plane, and a processing device which calculates equivalent veiling luminance on the basis of a pickup image of the imaging camera and calculates the value of a glare rating GR on the basis of the equivalent veiling luminance. The imaging camera has a super-wide-angle lens mounted thereon, and picks up an image in a position which is rotated within the horizontal plane by every angle corresponding to the angle of view ? of the super-wide-angle. The processing device combines pickup images to generate a composite image in which a glare measurement direction is set to the center of the composite image, calculates equivalent veiling luminance on the basis of the composite image, and calculates the value of the glare rating in the glare measurement direction.Type: ApplicationFiled: February 25, 2013Publication date: February 5, 2015Applicant: IWASAKI ELECTRIC CO., LTD.Inventors: Tetsuji Yamada, Kosuke Oshima
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Publication number: 20150022659Abstract: The luminance measuring apparatus for measuring the luminance of a road has an image pickup unit for picking up an image of the road, an input unit for inputting information concerning the road as an imaging target, and a luminance measuring unit for defining a luminance measurement target field A on the basis of the information input from the input unit and measuring the luminance within the luminance measurement target field A on the basis of an image picked up by the image pickup unit. The luminance measuring unit divides the luminance measurement target field A of the pickup image into a grid having a predetermined number of lattice intersection points MP in an equivalent of plan view, and allocates measurement points of luminance to the respective lattice intersection points MP.Type: ApplicationFiled: February 21, 2013Publication date: January 22, 2015Applicant: IWASAKI ELECTRIC CO., LTD.Inventors: Tetsuji Yamada, Kosuke Oshima
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Patent number: 7855413Abstract: A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.Type: GrantFiled: April 20, 2007Date of Patent: December 21, 2010Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Mizue Kitada, Kosuke Oshima, Toru Kurosaki, Shinji Kunori, Akihiko Sugai
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Publication number: 20070194364Abstract: A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.Type: ApplicationFiled: April 20, 2007Publication date: August 23, 2007Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Mizue Kitada, Kosuke Oshima, Toru Kurosaki, Shinji Kunori, Akihiko Sugai
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Patent number: 7230298Abstract: A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.Type: GrantFiled: July 18, 2002Date of Patent: June 12, 2007Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Mizue Kitada, Kosuke Oshima, Toru Kurosaki, Shinji Kunori, Akihiko Sugai
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Publication number: 20030042555Abstract: A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.Type: ApplicationFiled: July 18, 2002Publication date: March 6, 2003Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Mizue Kitada, Kosuke Oshima, Toru Kurosaki, Shinji Kunori, Akihiko Sugai