Abstract: A semiconductor device according to the present disclosure includes: a semiconductor substrate including at least: an n-type first semiconductor layer; an n-type second semiconductor layer on the first semiconductor layer; a p-type third semiconductor layer on the second semiconductor layer; and an n-type fourth semiconductor layer on an upper layer part of the third semiconductor layer; a plurality of first trench gates passing through the fourth to second semiconductor layers to reach an inner side of the first semiconductor layer; and a first main electrode having contact with the fourth semiconductor layer; wherein the plurality of first trench gates are disconnected in an electrode extraction region provided in a center part of the active region where main current flows, and are connected to the first main electrode in a first electrode extraction part connected to the first gate electrode in the disconnected part.

Abstract: An adjacent active trench in an IGBT region and an adjacent capacitance adjustment trench in a diode region are each provided in a stripe shape extending in a Y direction in a plan view. Each of a plurality of crossing trenches extends in an X direction orthogonal to the Y direction in a plan view and is provided in a stripe shape. Each of the plurality of crossing trenches is provided from the adjacent capacitance adjustment trench to the adjacent active trench in a plan view. Therefore, the gate electrode of the adjacent active trench and the capacitance adjustment electrode of the adjacent capacitance adjustment trench are electrically connected via the electrode for the crossing trench in the crossing trench.

Abstract: According to the disclosure, a semiconductor device includes a semiconductor substrate including an IGBT region and a diode region, a first electrode provided on an upper surface of the semiconductor substrate and a second electrode provided on a back surface of the semiconductor substrate, wherein the diode region includes an n-type drift layer, a p-type anode layer provided on an upper surface side of the drift layer, and an n-type cathode layer provided on a back surface side of the drift layer, a lifetime control region having crystal defect density higher than crystal defect density of other portions of the drift layer and including protons is provided on a back surface side relative to a center in a thickness direction of the semiconductor substrate among the drift layer, and a maximum value of donor concentration of the lifetime control region is equal to or less than 1.0×1015/cm3.