Patents by Inventor Kosuke Yanagidaira
Kosuke Yanagidaira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170062058Abstract: According to one embodiment, a semiconductor memory device comprises an input circuit configured to input data, a memory cell array which includes memory cells enabling data to be held and to which the input data is written, a control circuit configured to control operation of a memory relating to the data, and a training circuit configured to execute training of the input circuit in parallel with the operation of the memory.Type: ApplicationFiled: January 19, 2016Publication date: March 2, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kosuke YANAGIDAIRA, Shouichi OZAKI
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Patent number: 9583437Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.Type: GrantFiled: August 18, 2015Date of Patent: February 28, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kosuke Yanagidaira, Chikaaki Kodama
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Patent number: 9570182Abstract: According to one embodiment, a semiconductor memory device comprises an input circuit configured to input data, a memory cell array which includes memory cells enabling data to be held and to which the input data is written, a control circuit configured to control operation of a memory relating to the data, and a training circuit configured to execute training of the input circuit in parallel with the operation of the memory.Type: GrantFiled: January 19, 2016Date of Patent: February 14, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kosuke Yanagidaira, Shouichi Ozaki
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Patent number: 9564185Abstract: According to one embodiment, a semiconductor memory device includes a memory including a memory cell array, and an input/output pin configured to transfer data, a command, and an address from an external to the memory. The memory includes a termination circuit provided between the input/output pin and the memory cell array, and configured to supply a first voltage having a first amplitude in a first transfer mode and supply a second voltage having a second amplitude in a second transfer mode, a first intermediate value of the first amplitude being different from a second intermediate value of the second amplitude.Type: GrantFiled: January 19, 2016Date of Patent: February 7, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Kosuke Yanagidaira
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Patent number: 9520164Abstract: According to one embodiment, a ZQ calibration circuit comprises a replica buffer controller configured to apply electric stress to a replica buffer circuit with a circuit configuration substantially identical to a circuit configuration of an output buffer circuit according to a usage status of the output buffer circuit during a period when no calibration operation is performed.Type: GrantFiled: November 20, 2015Date of Patent: December 13, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kensuke Yamamoto, Kosuke Yanagidaira, Shouichi Ozaki
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Publication number: 20150357281Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.Type: ApplicationFiled: August 18, 2015Publication date: December 10, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kosuke YANAGIDAIRA, Chikaaki Kodama
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Patent number: 9209070Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.Type: GrantFiled: September 22, 2014Date of Patent: December 8, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kosuke Yanagidaira, Chikaaki Kodama
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Publication number: 20150253827Abstract: A control circuit of a semiconductor memory controls the semiconductor memory and configures a memory system with the semiconductor memory. The memory system is supplied with power from a power supply. The memory system transits between a first state and a second state in which a load current of the memory system is different from each other. The control circuit is configured to receive a terminal voltage of the power supply as a first terminal voltage when the memory system is in the first state. The control circuit is configured to receive a terminal voltage of the power supply as a second terminal voltage when the memory system is in the second state. The control circuit is configured to judge whether a difference between the first terminal voltage and the second terminal voltage is larger than a certain value.Type: ApplicationFiled: June 6, 2014Publication date: September 10, 2015Applicant: Kabushiki Kaisha ToshibaInventor: Kosuke YANAGIDAIRA
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Publication number: 20150041986Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.Type: ApplicationFiled: September 22, 2014Publication date: February 12, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kosuke YANAGIDAIRA, Chikaaki KODAMA
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Patent number: 8865583Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.Type: GrantFiled: October 31, 2012Date of Patent: October 21, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kosuke Yanagidaira, Chikaaki Kodama
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Publication number: 20140240037Abstract: A buffer circuit includes a first current mirror circuit, a second current mirror circuit, a first transistor, and a second transistor. The first current mirror circuit passes a first mirror current through a second node, corresponding to a first current passed through a first node, and is activated based on a first activating signal. The second current mirror circuit is connected to the first node and the second node, passes a second mirror current through the second node, corresponding to a second current passed through the first node, and is activated based on a second activating signal. The first transistor has a gate to which a reference voltage is applied and has a drain connected to the first node. The second transistor has a gate to which an input voltage is applied and has a drain connected to the second node.Type: ApplicationFiled: August 6, 2013Publication date: August 28, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Kosuke YANAGIDAIRA
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Patent number: 8816723Abstract: A buffer circuit includes a first current mirror circuit, a second current mirror circuit, a first transistor, and a second transistor. The first current mirror circuit passes a first mirror current through a second node, corresponding to a first current passed through a first node, and is activated based on a first activating signal. The second current mirror circuit is connected to the first node and the second node, passes a second mirror current through the second node, corresponding to a second current passed through the first node, and is activated based on a second activating signal. The first transistor has a gate to which a reference voltage is applied and has a drain connected to the first node. The second transistor has a gate to which an input voltage is applied and has a drain connected to the second node.Type: GrantFiled: August 6, 2013Date of Patent: August 26, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Kosuke Yanagidaira
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Patent number: 8742822Abstract: According to one embodiment, a first CMOS inverter receives an input signal corresponding to a first power supply voltage, and is driven by a second power supply voltage which is smaller than the first power supply voltage; a second CMOS inverter is connected to a rear stage of the first CMOS inverter, and is driven by the second power supply voltage; a first driving adjustment circuit adjusts a current driving force of a low level output of the first CMOS inverter; and a second driving adjustment circuit adjusts a current driving force of a low level output of the second CMOS inverter.Type: GrantFiled: January 29, 2013Date of Patent: June 3, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kosuke Yanagidaira, Shouichi Ozaki, Kenro Kubota
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Publication number: 20140049294Abstract: According to one embodiment, an input buffer includes a comparator that compares an input signal with a reference voltage, an inverter that inverts an output signal of the comparator, and a drive adjusting circuit that adjusts a current driving force of the inverter.Type: ApplicationFiled: January 30, 2013Publication date: February 20, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Kosuke YANAGIDAIRA
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Publication number: 20140049308Abstract: According to one embodiment, a first CMOS inverter receives an input signal corresponding to a first power supply voltage, and is driven by a second power supply voltage which is smaller than the first power supply voltage; a second CMOS inverter is connected to a rear stage of the first CMOS inverter, and is driven by the second power supply voltage; a first driving adjustment circuit adjusts a current driving force of a low level output of the first CMOS inverter; and a second driving adjustment circuit adjusts a current driving force of a low level output of the second CMOS inverter.Type: ApplicationFiled: January 29, 2013Publication date: February 20, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kosuke Yanagidaira, Shouichi Ozaki, Kenro Kubota
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Publication number: 20130164934Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.Type: ApplicationFiled: October 31, 2012Publication date: June 27, 2013Inventors: Kosuke YANAGIDAIRA, Chikaaki KODAMA
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Patent number: 8298928Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.Type: GrantFiled: December 11, 2008Date of Patent: October 30, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Kosuke Yanagidaira, Chikaaki Kodama
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Patent number: 7952958Abstract: There is provided a non-volatile memory having electrically rewritable non-volatile memory cells arranged therein. A controller controls operation at the non-volatile memory. The non-volatile memory comprises a status output section configured to output status information indicating a status of read operation, write operation or erase operation in the non-volatile memory cell. The controller comprises a control signal generating section configured to output a control signal for a certain operation in the non-volatile memory, and a control signal switching section configured to instruct the control signal generating section to switch the control signal based on the status information.Type: GrantFiled: July 22, 2009Date of Patent: May 31, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kosuke Yanagidaira, Toshihiro Suzuki, Naoya Tokiwa
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Patent number: 7948796Abstract: The present invention provides a semiconductor memory device that can minimize the widening of the threshold voltage distribution of cell transistors during a data erasing operation.Type: GrantFiled: June 4, 2009Date of Patent: May 24, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tomofumi Fujimura, Kosuke Yanagidaira
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Patent number: 7889565Abstract: A nonvolatile semiconductor memory device includes a plurality of memory cells, a read/program circuit which supplies a program voltage and a program verification voltage to the plurality of memory cells and desired data is programmed, supplies a first program verification voltage to the plurality of memory cells and then supplies a second program verification voltage to the plurality of memory cells when programming the data, and a read/program control circuit which determines memory cells which reach a first data program state and memory cells which do not reach the first data program state when supplying the first program verification voltage, and determines memory cells which reach a second data program state and memory cells which do not reach the second data program state when supplying the second program verification voltage, and supplies a program control voltage which changes the program operation state for each memory cell.Type: GrantFiled: March 20, 2009Date of Patent: February 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kosuke Yanagidaira, Toshihiro Suzuki