Patents by Inventor Kosuke Yayama
Kosuke Yayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230195159Abstract: A technique capable of detecting a substrate bias voltage at a low power consumption is provided. The technique including: a voltage boost circuit outputting a boost voltage based on a first clock signal having a first frequency; a voltage drop circuit outputting a drop voltage based on a second clock signal having a second frequency; and a logic circuit block comparing the first frequency and the second frequency and outputting a comparison result between the first frequency and the second frequency in accordance with predetermined criteria is provided.Type: ApplicationFiled: November 28, 2022Publication date: June 22, 2023Inventor: Kosuke YAYAMA
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Patent number: 11450731Abstract: A resistance element includes a conductor, the conductor having a repeating pattern of: a first conductive layer formed on a first interlayer insulating layer on a semiconductor substrate; a second conductive layer formed on a second interlayer insulating layer different from the first interlayer insulating layer; and an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the second conductive layer has a resistance-value fluctuation characteristic opposite to a resistance-value fluctuation characteristic of the first conductive layer after a heat treatment.Type: GrantFiled: January 21, 2021Date of Patent: September 20, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Chiemi Hashimoto, Kosuke Yayama, Hidekazu Tawara
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Patent number: 11394371Abstract: The polysilicon resistance has a large resistance variation rate after the end of the mold packaging process. In order to enable high-precision trimming, it is desired to realize a resistance which is hardly affected by stress and temperature fluctuation generated in a substrate by a mold packaging process. A resistance element is formed in a plurality of wiring layers, and has a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and a repeating pattern of an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the interlayer conductive layer is formed of a plurality of types of materials.Type: GrantFiled: August 7, 2019Date of Patent: July 19, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Chiemi Hashimoto, Kosuke Yayama, Tomokazu Matsuzaki
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Publication number: 20210257443Abstract: A resistance element includes a conductor, the conductor having a repeating pattern of: a first conductive layer formed on a first interlayer insulating layer on a semiconductor substrate; a second conductive layer formed on a second interlayer insulating layer different from the first interlayer insulating layer; and an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the second conductive layer has a resistance-value fluctuation characteristic opposite to a resistance-value fluctuation characteristic of the first conductive layer after a heat treatment.Type: ApplicationFiled: January 21, 2021Publication date: August 19, 2021Inventors: Chiemi HASHIMOTO, Kosuke YAYAMA, Hidekazu TAWARA
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Patent number: 10958250Abstract: A polycrystalline silicon resistor is large in coefficient of fluctuation in resistance between before and after the completion of a package molding process. To enable highly accurate trimming, it is desired to implement a resistor that is hardly subjected to stress produced in a substrate during a package molding process. A resistance element is formed of a plurality of wiring layers and has a repetitive pattern of a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together.Type: GrantFiled: June 8, 2018Date of Patent: March 23, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Chiemi Hashimoto, Kosuke Yayama, Katsumi Tsuneno, Tomokazu Matsuzaki
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Publication number: 20200076409Abstract: The polysilicon resistance has a large resistance variation rate after the end of the mold packaging process. In order to enable high-precision trimming, it is desired to realize a resistance which is hardly affected by stress and temperature fluctuation generated in a substrate by a mold packaging process. A resistance element is formed in a plurality of wiring layers, and has a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and a repeating pattern of an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the interlayer conductive layer is formed of a plurality of types of materials.Type: ApplicationFiled: August 7, 2019Publication date: March 5, 2020Inventors: Chiemi HASHIMOTO, Kosuke YAYAMA, Tomokazu MATSUZAKI
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Patent number: 10530297Abstract: A semiconductor device includes a reference voltage generation circuit configured to generate reference voltages Va and Vb capable of adjusting a primary temperature characteristic, and an oscillation circuit configured to output an oscillation signal using the reference voltages Va and Vb, in which the oscillation circuit includes a frequency/current conversion circuit that is driven by the reference voltage Va and outputs a current Ie in accordance with a frequency of a feedback signal, a control voltage generation circuit configured to generate a control voltage in accordance with a potential difference between a voltage in accordance with the current Ie and the reference voltage Vb, a voltage control oscillation circuit configured to output the oscillation signal having a frequency in accordance with the control voltage, and a frequency division circuit configured to divide a frequency of the oscillation signal and output the resulting signal as the feedback signal.Type: GrantFiled: March 22, 2018Date of Patent: January 7, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Guoqiang Zhang, Kosuke Yayama
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Publication number: 20180375497Abstract: A polycrystalline silicon resistor is large in coefficient of fluctuation in resistance between before and after the completion of a package molding process. To enable highly accurate trimming, it is desired to implement a resistor that is hardly subjected to stress produced in a substrate during a package molding process. A resistance element is formed of a plurality of wiring layers and has a repetitive pattern of a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together.Type: ApplicationFiled: June 8, 2018Publication date: December 27, 2018Inventors: Chiemi HASHIMOTO, Kosuke YAYAMA, Katsumi TSUNENO, Tomokazu MATSUZAKI
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Publication number: 20180351509Abstract: A semiconductor device includes a reference voltage generation circuit configured to generate reference voltages Va and Vb capable of adjusting a primary temperature characteristic, and an oscillation circuit configured to output an oscillation signal using the reference voltages Va and Vb, in which the oscillation circuit includes a frequency/current conversion circuit that is driven by the reference voltage Va and outputs a current Ie in accordance with a frequency of a feedback signal, a control voltage generation circuit configured to generate a control voltage in accordance with a potential difference between a voltage in accordance with the current Ie and the reference voltage Vb, a voltage control oscillation circuit configured to output the oscillation signal having a frequency in accordance with the control voltage, and a frequency division circuit configured to divide a frequency of the oscillation signal and output the resulting signal as the feedback signal.Type: ApplicationFiled: March 22, 2018Publication date: December 6, 2018Inventors: Guoqiang ZHANG, Kosuke YAYAMA
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Patent number: 9829911Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.Type: GrantFiled: January 27, 2016Date of Patent: November 28, 2017Assignee: Renesas Electronics CorporationInventors: Kosuke Yayama, Takashi Nakamura
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Patent number: 9587994Abstract: There is provided a semiconductor device which can provide desired output characteristics suitable to applications. A semiconductor device 10 includes a temperature sensing unit 11 which generates an analog sensing signal corresponding to a temperature, and an AD converter unit 12 which converts the analog sensing signal into a digital output signal corresponding to an adjusted temperature change rate based on a temperature change rate adjustment signal for adjusting the temperature change rate. The temperature change rate refers to a change in a detected temperature per bit of a digital output signal.Type: GrantFiled: July 22, 2015Date of Patent: March 7, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Kosuke Yayama
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Publication number: 20160164529Abstract: A frequency-locked loop circuit includes a digital control oscillator that generates a clock, and an FLL (frequency-locked loop) controller that generates a frequency control code to control an oscillation frequency of the clock. The FLL controller includes a frequency comparison unit that compares a frequency of a clock generated by the digital control oscillator with a frequency of a multiplied reference clock, and a delay code control unit that generates, based on a comparison result of the frequency comparison unit, the frequency control code so that the frequency of the clock generated by the digital control oscillator matches the frequency of the multiplied reference clock, the frequency comparison unit determines the frequency of the clock, and the delay code control unit generates the frequency control code according to a determination result of the frequency comparison unit, and outputs the frequency control code to the digital control oscillator.Type: ApplicationFiled: February 12, 2016Publication date: June 9, 2016Inventors: Takashi Nakamura, Kosuke YAYAMA, Masaaki IIJIMA
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Publication number: 20160139623Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.Type: ApplicationFiled: January 27, 2016Publication date: May 19, 2016Inventors: Kosuke YAYAMA, Takashi NAKAMURA
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Patent number: 9281780Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.Type: GrantFiled: December 4, 2014Date of Patent: March 8, 2016Assignee: Renesas Electronics CorporationInventors: Kosuke Yayama, Takashi Nakamura
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Patent number: 9276585Abstract: A frequency-locked loop circuit has a digital control oscillator that generates a clock, and an FLL controller that generates a frequency control code to control an oscillation frequency of the clock. The FLL controller has a frequency comparison unit and a delay code control unit. The frequency comparison unit compares a frequency of a clock generated by the digital control oscillator with a frequency of a multiplied reference clock. The delay code control unit generates, based on a comparison result of the frequency comparison unit, the frequency control code so that the frequency of the clock generated by the digital control oscillator matches the frequency of the multiplied reference clock. The frequency comparison unit determines the frequency of the clock by using first and second thresholds. The delay code control unit generates the frequency control code according to a determination of the frequency comparison unit.Type: GrantFiled: April 3, 2014Date of Patent: March 1, 2016Assignee: Renesas Electronics CorporationInventors: Takashi Nakamura, Kosuke Yayama, Masaaki Iijima
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Publication number: 20160054183Abstract: There is provided a semiconductor device which can provide desired output characteristics suitable to applications. A semiconductor device 10 includes a temperature sensing unit 11 which generates an analog sensing signal corresponding to a temperature, and an AD converter unit 12 which converts the analog sensing signal into a digital output signal corresponding to an adjusted temperature change rate based on a temperature change rate adjustment signal for adjusting the temperature change rate. The temperature change rate refers to a change in a detected temperature per bit of a digital output signal.Type: ApplicationFiled: July 22, 2015Publication date: February 25, 2016Inventor: Kosuke YAYAMA
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Publication number: 20150162874Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.Type: ApplicationFiled: December 4, 2014Publication date: June 11, 2015Inventors: Kosuke Yayama, Takashi Nakamura
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Patent number: 8970266Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.Type: GrantFiled: October 30, 2013Date of Patent: March 3, 2015Assignee: Renesas Electronics CorporationInventors: Kosuke Yayama, Takashi Nakamura
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Publication number: 20140312981Abstract: A frequency-locked loop circuit includes: a digital control oscillator that generates a clock; and an FLL controller that generates a frequency control code to control an oscillation frequency of the clock. The FLL controller includes: a frequency comparison unit that compares a frequency of a clock generated by the digital control oscillator with a frequency of a multiplied reference clock; and a delay code control unit that generates, based on a comparison result of the frequency comparison unit, the frequency control code so that the frequency of the clock generated by the digital control oscillator matches the frequency of the multiplied reference clock. The frequency comparison unit determines the frequency of the clock by using first and second thresholds. The delay code control unit generates the frequency control code according to a determination of the frequency comparison unit and outputs the frequency control code to the digital control oscillator.Type: ApplicationFiled: April 3, 2014Publication date: October 23, 2014Applicant: Renesas Electronics CorporationInventors: Takashi NAKAMURA, Kosuke YAYAMA, Masaaki IIJIMA
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Patent number: 8736337Abstract: A clock signal capable of changing the frequency in a wide range and with high resolution is generated. An operational amplifier AMP1 is subject to feedback control so that the voltage of a positive input part equals that of a negative input part. The voltage of a circuit node fbck equals a reference voltage VREFI. A decoder DEC decodes control signals CNT7 and CNT6 and turns on one of transistors T2 to T5. This configuration provides feedback control so that the voltage of the circuit node fbck equals the reference voltage VREFI. This significantly reduces the on-resistances of the transistors T2 to T5 and prevents the degradation of the frequency accuracy.Type: GrantFiled: December 21, 2011Date of Patent: May 27, 2014Assignee: Renesas Electronics CorporationInventors: Kosuke Yayama, Takashi Nakamura