Patents by Inventor Kosuke Yayama

Kosuke Yayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10530297
    Abstract: A semiconductor device includes a reference voltage generation circuit configured to generate reference voltages Va and Vb capable of adjusting a primary temperature characteristic, and an oscillation circuit configured to output an oscillation signal using the reference voltages Va and Vb, in which the oscillation circuit includes a frequency/current conversion circuit that is driven by the reference voltage Va and outputs a current Ie in accordance with a frequency of a feedback signal, a control voltage generation circuit configured to generate a control voltage in accordance with a potential difference between a voltage in accordance with the current Ie and the reference voltage Vb, a voltage control oscillation circuit configured to output the oscillation signal having a frequency in accordance with the control voltage, and a frequency division circuit configured to divide a frequency of the oscillation signal and output the resulting signal as the feedback signal.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: January 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Guoqiang Zhang, Kosuke Yayama
  • Publication number: 20180375497
    Abstract: A polycrystalline silicon resistor is large in coefficient of fluctuation in resistance between before and after the completion of a package molding process. To enable highly accurate trimming, it is desired to implement a resistor that is hardly subjected to stress produced in a substrate during a package molding process. A resistance element is formed of a plurality of wiring layers and has a repetitive pattern of a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together.
    Type: Application
    Filed: June 8, 2018
    Publication date: December 27, 2018
    Inventors: Chiemi HASHIMOTO, Kosuke YAYAMA, Katsumi TSUNENO, Tomokazu MATSUZAKI
  • Publication number: 20180351509
    Abstract: A semiconductor device includes a reference voltage generation circuit configured to generate reference voltages Va and Vb capable of adjusting a primary temperature characteristic, and an oscillation circuit configured to output an oscillation signal using the reference voltages Va and Vb, in which the oscillation circuit includes a frequency/current conversion circuit that is driven by the reference voltage Va and outputs a current Ie in accordance with a frequency of a feedback signal, a control voltage generation circuit configured to generate a control voltage in accordance with a potential difference between a voltage in accordance with the current Ie and the reference voltage Vb, a voltage control oscillation circuit configured to output the oscillation signal having a frequency in accordance with the control voltage, and a frequency division circuit configured to divide a frequency of the oscillation signal and output the resulting signal as the feedback signal.
    Type: Application
    Filed: March 22, 2018
    Publication date: December 6, 2018
    Inventors: Guoqiang ZHANG, Kosuke YAYAMA
  • Patent number: 9829911
    Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: November 28, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kosuke Yayama, Takashi Nakamura
  • Patent number: 9587994
    Abstract: There is provided a semiconductor device which can provide desired output characteristics suitable to applications. A semiconductor device 10 includes a temperature sensing unit 11 which generates an analog sensing signal corresponding to a temperature, and an AD converter unit 12 which converts the analog sensing signal into a digital output signal corresponding to an adjusted temperature change rate based on a temperature change rate adjustment signal for adjusting the temperature change rate. The temperature change rate refers to a change in a detected temperature per bit of a digital output signal.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: March 7, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kosuke Yayama
  • Publication number: 20160164529
    Abstract: A frequency-locked loop circuit includes a digital control oscillator that generates a clock, and an FLL (frequency-locked loop) controller that generates a frequency control code to control an oscillation frequency of the clock. The FLL controller includes a frequency comparison unit that compares a frequency of a clock generated by the digital control oscillator with a frequency of a multiplied reference clock, and a delay code control unit that generates, based on a comparison result of the frequency comparison unit, the frequency control code so that the frequency of the clock generated by the digital control oscillator matches the frequency of the multiplied reference clock, the frequency comparison unit determines the frequency of the clock, and the delay code control unit generates the frequency control code according to a determination result of the frequency comparison unit, and outputs the frequency control code to the digital control oscillator.
    Type: Application
    Filed: February 12, 2016
    Publication date: June 9, 2016
    Inventors: Takashi Nakamura, Kosuke YAYAMA, Masaaki IIJIMA
  • Publication number: 20160139623
    Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.
    Type: Application
    Filed: January 27, 2016
    Publication date: May 19, 2016
    Inventors: Kosuke YAYAMA, Takashi NAKAMURA
  • Patent number: 9281780
    Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: March 8, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kosuke Yayama, Takashi Nakamura
  • Patent number: 9276585
    Abstract: A frequency-locked loop circuit has a digital control oscillator that generates a clock, and an FLL controller that generates a frequency control code to control an oscillation frequency of the clock. The FLL controller has a frequency comparison unit and a delay code control unit. The frequency comparison unit compares a frequency of a clock generated by the digital control oscillator with a frequency of a multiplied reference clock. The delay code control unit generates, based on a comparison result of the frequency comparison unit, the frequency control code so that the frequency of the clock generated by the digital control oscillator matches the frequency of the multiplied reference clock. The frequency comparison unit determines the frequency of the clock by using first and second thresholds. The delay code control unit generates the frequency control code according to a determination of the frequency comparison unit.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: March 1, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Nakamura, Kosuke Yayama, Masaaki Iijima
  • Publication number: 20160054183
    Abstract: There is provided a semiconductor device which can provide desired output characteristics suitable to applications. A semiconductor device 10 includes a temperature sensing unit 11 which generates an analog sensing signal corresponding to a temperature, and an AD converter unit 12 which converts the analog sensing signal into a digital output signal corresponding to an adjusted temperature change rate based on a temperature change rate adjustment signal for adjusting the temperature change rate. The temperature change rate refers to a change in a detected temperature per bit of a digital output signal.
    Type: Application
    Filed: July 22, 2015
    Publication date: February 25, 2016
    Inventor: Kosuke YAYAMA
  • Publication number: 20150162874
    Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.
    Type: Application
    Filed: December 4, 2014
    Publication date: June 11, 2015
    Inventors: Kosuke Yayama, Takashi Nakamura
  • Patent number: 8970266
    Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: March 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kosuke Yayama, Takashi Nakamura
  • Publication number: 20140312981
    Abstract: A frequency-locked loop circuit includes: a digital control oscillator that generates a clock; and an FLL controller that generates a frequency control code to control an oscillation frequency of the clock. The FLL controller includes: a frequency comparison unit that compares a frequency of a clock generated by the digital control oscillator with a frequency of a multiplied reference clock; and a delay code control unit that generates, based on a comparison result of the frequency comparison unit, the frequency control code so that the frequency of the clock generated by the digital control oscillator matches the frequency of the multiplied reference clock. The frequency comparison unit determines the frequency of the clock by using first and second thresholds. The delay code control unit generates the frequency control code according to a determination of the frequency comparison unit and outputs the frequency control code to the digital control oscillator.
    Type: Application
    Filed: April 3, 2014
    Publication date: October 23, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Takashi NAKAMURA, Kosuke YAYAMA, Masaaki IIJIMA
  • Patent number: 8736337
    Abstract: A clock signal capable of changing the frequency in a wide range and with high resolution is generated. An operational amplifier AMP1 is subject to feedback control so that the voltage of a positive input part equals that of a negative input part. The voltage of a circuit node fbck equals a reference voltage VREFI. A decoder DEC decodes control signals CNT7 and CNT6 and turns on one of transistors T2 to T5. This configuration provides feedback control so that the voltage of the circuit node fbck equals the reference voltage VREFI. This significantly reduces the on-resistances of the transistors T2 to T5 and prevents the degradation of the frequency accuracy.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: May 27, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kosuke Yayama, Takashi Nakamura
  • Publication number: 20140118060
    Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.
    Type: Application
    Filed: October 30, 2013
    Publication date: May 1, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Kosuke Yayama, Takashi Nakamura
  • Patent number: 8692584
    Abstract: A frequency-voltage converting circuit 13 is composed of a switch unit including switches SW1 and SW2, electrostatic capacitive elements C and C10 to C13, and switches CSW0 to CSW3. The electrostatic capacitive elements C10 to C13 are composed of elements having mutually different absolute values of capacitance and are provided so as to cover a frequency range intended by a designer. The electrostatic capacitance values are weighted by, for example, 2. The electrostatic capacitive elements C11 to C13 are selected by, for example, the switches CSW0 to CSW3 based on 4-bit frequency adjustment control signals SELC0 to SELC3, thereby carrying out frequency switching.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: April 8, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Nakamura, Kosuke Yayama
  • Patent number: 8368472
    Abstract: A high-accuracy clock signal is generated even when the settings of the clock frequency are changed or there is a variation in power supply, temperature, or the like. A frequency-voltage conversion circuit includes a switch portion including switches, electrostatic capacitive elements, and other switches. The electrostatic capacitive elements have different absolute capacitance values, and are provided so as to cover a frequency range intended by a designer. For example, based on 4-bit frequency adjustment control signals, the other switches select the electrostatic capacitive elements having the electrostatic capacitance values thereof each weighted with 2 to perform the switching of a frequency.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: February 5, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Nakamura, Kosuke Yayama
  • Publication number: 20120319738
    Abstract: A frequency-voltage converting circuit 13 is composed of a switch unit including switches SW1 and SW2, electrostatic capacitive elements C and C10 to C13, and switches CSW0 to CSW3. The electrostatic capacitive elements C10 to C13 are composed of elements having mutually different absolute values of capacitance and are provided so as to cover a frequency range intended by a designer. The electrostatic capacitance values are weighted by, for example, 2. The electrostatic capacitive elements C11 to C13 are selected by, for example, the switches CSW0 to CSW3 based on 4-bit frequency adjustment control signals SELC0 to SELC3, thereby carrying out frequency switching.
    Type: Application
    Filed: February 19, 2010
    Publication date: December 20, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Nakamura, Kosuke Yayama
  • Publication number: 20120161868
    Abstract: A clock signal capable of changing the frequency in a wide range and with high resolution is generated. An operational amplifier AMP1 is subject to feedback control so that the voltage of a positive input part equals that of a negative input part. The voltage of a circuit node fbck equals a reference voltage VREFI. A decoder DEC decodes control signals CNT7 and CNT6 and turns on one of transistors T2 to T5. This configuration provides feedback control so that the voltage of the circuit node fbck equals the reference voltage VREFI. This significantly reduces the on-resistances of the transistors T2 to T5 and prevents the degradation of the frequency accuracy.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 28, 2012
    Inventors: Kosuke YAYAMA, Takashi Nakamura
  • Publication number: 20120074986
    Abstract: A high-accuracy clock signal is generated even when the settings of the clock frequency are changed or there is a variation in power supply, temperature, or the like. A frequency-voltage conversion circuit includes a switch portion including switches, electrostatic capacitive elements, and other switches. The electrostatic capacitive elements have different absolute capacitance values, and are provided so as to cover a frequency range intended by a designer. For example, based on 4-bit frequency adjustment control signals, the other switches select the electrostatic capacitive elements having the electrostatic capacitance values thereof each weighted with 2 to perform the switching of a frequency.
    Type: Application
    Filed: January 24, 2011
    Publication date: March 29, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi NAKAMURA, Kosuke YAYAMA