Patents by Inventor Kota JINNO

Kota JINNO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device including a plurality of bonding pads
    Patent number: 11211349
    Abstract: A semiconductor device comprising: bonding pads formed in the first wiring layer; and first wirings and a second wiring formed in a second wiring layer provided one layer below the first wiring layer. Here, a power supply potential and a reference potential are to be supplied to each first wiring and the second wiring, respectively. Also, in transparent plan view, each of the first wirings is arranged next to each other, and is arranged at a first position of the second wiring layer, that is overlapped with the bonding region of the first bonding pad. Also, in transparent plan view, the second wiring is arranged at a second position of the second wiring layer, that is overlapped with a first region located between the first bonding pad and the second bonding pad. Further, a width of each first wiring is less than a width of the second wiring.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: December 28, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seiya Isozaki, Tatsuya Kobayashi, Kota Jinno
  • SEMICONDUCTOR DEVICE
    Publication number: 20210057361
    Abstract: A semiconductor device comprising: bonding pads formed in the first wiring layer; and first wirings and a second wiring formed in a second wiring layer provided one layer below the first wiring layer. Here, a power supply potential and a reference potential are to be supplied to each first wiring and the second wiring, respectively. Also, in transparent plan view, each of the first wirings is arranged next to each other, and is arranged at a first position of the second wiring layer, that is overlapped with the bonding region of the first bonding pad. Also, in transparent plan view, the second wiring is arranged at a second position of the second wiring layer, that is overlapped with a first region located between the first bonding pad and the second bonding pad. Further, a width of each first wiring is less than a width of the second wiring.
    Type: Application
    Filed: June 24, 2020
    Publication date: February 25, 2021
    Inventors: Seiya ISOZAKI, Tatsuya KOBAYASHI, Kota JINNO