Patents by Inventor Kota YASUNISHI
Kota YASUNISHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11610779Abstract: An ion implanted region is formed by implanting Mg ions into a predetermined region of the surface of the first p-type layer. Subsequently, a second n-type layer is formed on the first p-type layer and the ion implanted region. A trench is formed by dry etching a predetermined region of the surface of the second n-type layer until reaching the first n-type layer. Next, heat treatment is performed to diffuse Mg. Thus, a p-type impurity region is formed in a region with a predetermined depth from the surface of the first n-type layer below the ion implanted region. Since the trench is formed before the heat treatment, Mg is not diffused laterally beyond the trench. Therefore, the width of the p-type impurity region is almost the same as the width of the first p-type layer divided by the trench.Type: GrantFiled: January 26, 2021Date of Patent: March 21, 2023Assignee: TOYODA GOSEI CO., LTD.Inventors: Kota Yasunishi, Yukihisa Ueno
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Publication number: 20210257216Abstract: An ion implanted region is formed by implanting Mg ions into a predetermined region of the surface of the first p-type layer. Subsequently, a second n-type layer is formed on the first p-type layer and the ion implanted region. A trench is formed by dry etching a predetermined region of the surface of the second n-type layer until reaching the first n-type layer. Next, heat treatment is performed to diffuse Mg. Thus, a p-type impurity region is formed in a region with a predetermined depth from the surface of the first n-type layer below the ion implanted region. Since the trench is formed before the heat treatment, Mg is not diffused laterally beyond the trench. Therefore, the width of the p-type impurity region is almost the same as the width of the first p-type layer divided by the trench.Type: ApplicationFiled: January 26, 2021Publication date: August 19, 2021Inventors: Kota YASUNISHI, Yukihisa UENO
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Patent number: 11011607Abstract: The likelihood of formation of a corner resulting from a recess in a part of an n-type semiconductor layer is reduced at a deeper position than a p-type semiconductor layer. A method of manufacturing a semiconductor device comprises: forming a gallium nitride (GaN) based n-type semiconductor layer containing n-type impurities; forming a groove by forming a first mask on a part of a surface of the n-type semiconductor layer and then etching a part uncovered by the first mask; removing the first mask; forming a gallium nitride (GaN) based p-type semiconductor layer containing p-type impurities on the surface of the n-type semiconductor layer including the groove; etching the p-type semiconductor layer so as to expose the n-type semiconductor layer at least in a range differing from a range in the presence of the groove; and forming a metal electrode contacting the exposed n-type semiconductor layer and the p-type semiconductor layer.Type: GrantFiled: September 17, 2019Date of Patent: May 18, 2021Assignee: TOYODA GOSEI CO., LTD.Inventors: Kota Yasunishi, Toru Oka, Kazuya Hasegawa
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Patent number: 10832911Abstract: An n-type GaN layer, a p-type diffusion region formed by ion implantation and annealing in a part of the n-type layer, and a Schottky electrode are formed on the n-type layer. A region without the p-type region is defined as region A, and a region with the p-type region is defined as region B. In region A, an average density of each electron trap level of the n-type layer in a region having a depth of 0.8 ?m to 1.6 ?m on the n-type layer side is set so as to satisfy the predetermined conditions. In region B, an average density of each carrier trap level of the n-type layer in a region having a depth of 0.8 ?m to 1.6 ?m on the n-type layer side from a boundary between the n-type layer and the p-type diffusion region is set so as to satisfy the predetermined conditions.Type: GrantFiled: August 29, 2019Date of Patent: November 10, 2020Assignee: TOYODA GOSEI CO., LTD.Inventors: Nariaki Tanaka, Toru Oka, Yukihisa Ueno, Kota Yasunishi
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Patent number: 10679861Abstract: A manufacturing method of a semiconductor device comprises forming an ohmic electrode on a surface of a semiconductor substrate, the ohmic electrode including an aluminum layer in a side opposite to a side in contact with the semiconductor substrate, performing a heat treatment on the ohmic electrode, performing an acid treatment on a surface of the aluminum layer in the ohmic electrode that has been subjected to the heat treatment and forming a wiring electrode in the side of the aluminum layer opposite to the side where the semiconductor substrate is provided after the acid treatment.Type: GrantFiled: March 14, 2018Date of Patent: June 9, 2020Assignee: TOYODA GOSEI CO., LTD.Inventor: Kota Yasunishi
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Publication number: 20200098872Abstract: The likelihood of formation of a corner resulting from a recess in a part of an n-type semiconductor layer is reduced at a deeper position than a p-type semiconductor layer. A method of manufacturing a semiconductor device comprises: forming a gallium nitride (GaN) based n-type semiconductor layer containing n-type impurities; forming a groove by forming a first mask on a part of a surface of the n-type semiconductor layer and then etching a part uncovered by the first mask; removing the first mask; forming a gallium nitride (GaN) based p-type semiconductor layer containing p-type impurities on the surface of the n-type semiconductor layer including the groove; etching the p-type semiconductor layer so as to expose the n-type semiconductor layer at least in a range differing from a range in the presence of the groove; and forming a metal electrode contacting the exposed n-type semiconductor layer and the p-type semiconductor layer.Type: ApplicationFiled: September 17, 2019Publication date: March 26, 2020Inventors: Kota YASUNISHI, Toru Oka, Kazuya Hasegawa
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Publication number: 20200098565Abstract: An n-type GaN layer, a p-type diffusion region formed by ion implantation and annealing in a part of the n-type layer, and a Schottky electrode are formed on the n-type layer. A region without the p-type region is defined as region A, and a region with the p-type region is defined as region B. In region A, an average density of each electron trap level of the n-type layer in a region having a depth of 0.8 ?m to 1.6 ?m on the n-type layer side is set so as to satisfy the predetermined conditions. In region B, an average density of each carrier trap level of the n-type layer in a region having a depth of 0.8 ?m to 1.6 ?m on the n-type layer side from a boundary between the n-type layer and the p-type diffusion region is set so as to satisfy the predetermined conditions.Type: ApplicationFiled: August 29, 2019Publication date: March 26, 2020Inventors: Nariaki Tanaka, Toru Oka, Yukihisa Ueno, Kota Yasunishi
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Publication number: 20180277375Abstract: A manufacturing method of a semiconductor device comprises forming an ohmic electrode on a surface of a semiconductor substrate, the ohmic electrode including an aluminum layer in a side opposite to a side in contact with the semiconductor substrate, performing a heat treatment on the ohmic electrode, performing an acid treatment on a surface of the aluminum layer in the ohmic electrode that has been subjected to the heat treatment and forming a wiring electrode in the side of the aluminum layer opposite to the side where the semiconductor substrate is provided after the acid treatment.Type: ApplicationFiled: March 14, 2018Publication date: September 27, 2018Inventor: Kota YASUNISHI
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Patent number: 9741578Abstract: A technique of reducing the contact resistance between a semiconductor substrate and a metal layer is provided. A manufacturing method of a semiconductor device comprises a process of forming a metal layer on an N surface of a nitride semiconductor substrate. The process of forming the metal layer includes a first process of forming a metal layer by sputtering at a film formation rate controlled to 4 nm/minute or lower.Type: GrantFiled: February 3, 2015Date of Patent: August 22, 2017Assignee: TOYODA GOSEI CO., LTD.Inventors: Kota Yasunishi, Tohru Oka, Noriaki Murakami
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Publication number: 20150228493Abstract: A technique of reducing the contact resistance between a semiconductor substrate and a metal layer is provided. A manufacturing method of a semiconductor device comprises a process of forming a metal layer on an N surface of a nitride semiconductor substrate. The process of forming the metal layer includes a first process of forming a metal layer by sputtering at a film formation rate controlled to 4 nm/minute or lower.Type: ApplicationFiled: February 3, 2015Publication date: August 13, 2015Inventors: Kota YASUNISHI, Tohru Oka, Noriaki Murakami