Patents by Inventor Kotaro Kato
Kotaro Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11243674Abstract: A display apparatus includes a display section that displays an image containing one or more objects based on display image data on a display surface, a position generator that generates information representing the position of a mobile terminal that comes into contact with the display surface as terminal position information representing a terminal position in the image, an object identifier that identifies object data on an object corresponding to the terminal position based on the display image data and the terminal position information, and a transmitter that transmits the object data to the mobile terminal.Type: GrantFiled: July 9, 2019Date of Patent: February 8, 2022Assignee: SEIKO EPSON CORPORATIONInventor: Kotaro Kato
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Publication number: 20200019297Abstract: A display apparatus includes a display section that displays an image containing one or more objects based on display image data on a display surface, a position generator that generates information representing the position of a mobile terminal that comes into contact with the display surface as terminal position information representing a terminal position in the image, an object identifier that identifies object data on an object corresponding to the terminal position based on the display image data and the terminal position information, and a transmitter that transmits the object data to the mobile terminal.Type: ApplicationFiled: July 9, 2019Publication date: January 16, 2020Applicant: SEIKO EPSON CORPORATIONInventor: Kotaro KATO
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Patent number: 9304606Abstract: An image display system includes: an image display unit that displays an image indicated by image data on a display surface; a trajectory data generation unit that specifies a position on the display surface indicated by a pointer and generates trajectory data indicating a trajectory of the pointer; and a trajectory data processing unit that performs processing in a mode corresponding to the pointer for the trajectory data generated by the trajectory data generation unit, wherein the image display unit displays an image of a trajectory, which is indicated by the trajectory data generated by the trajectory data generation unit, on the display surface.Type: GrantFiled: May 7, 2013Date of Patent: April 5, 2016Assignee: SEIKO EPSON CORPORATIONInventors: Koji Endo, Kotaro Kato
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Publication number: 20130300658Abstract: An image display system includes: an image display unit that displays an image indicated by image data on a display surface; a trajectory data generation unit that specifies a position on the display surface indicated by a pointer and generates trajectory data indicating a trajectory of the pointer; and a trajectory data processing unit that performs processing in a mode corresponding to the pointer for the trajectory data generated by the trajectory data generation unit, wherein the image display unit displays an image of a trajectory, which is indicated by the trajectory data generated by the trajectory data generation unit, on the display surface.Type: ApplicationFiled: May 7, 2013Publication date: November 14, 2013Applicant: SEIKO EPSON CORPORATIONInventors: Koji ENDO, Kotaro KATO
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Patent number: 5188881Abstract: A thermosensitive stencil paper is composed of a substrate and a thermoplastic resin film formed thereon, which thermoplastic resin film has projections in the surface portion thereof, with a printing roughness (R.sub.p) of 2.2 to 5.0 .mu.m, which is a physical quantity proportional to the average depth of the depressions in the surface portion thereof pressed against a standard surface.Type: GrantFiled: June 20, 1991Date of Patent: February 23, 1993Assignees: Ricoh Company, Ltd., Teijin Ltd.Inventors: Shoichi Sugiyama, Fumiaki Arai, Masayasu Nonogaki, Yuji Natori, Hideyuki Yamaguchi, Hitoshi Ueda, Hiroshi Tomita, Kotaro Kato
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Patent number: 4639548Abstract: An error correction code data communication system scrambles and descrambles both non-coded data and coded data by using substantially the same code process at the opposite ends of a transmission path. The frequency of the occurrence of an error correction pulse in a decoder is monitored to set up synchronization for descrambling. The transmitter includes an encoder for adding a correction code to a data signal to be transmitted, and a scrambler for randomizing the data signal. The receiver includes a descrambler for descrambling the data signal which was randomized by the scrambler, and a decoder for correcting a code error responsive to the error correction code. The scrambler modulo 2 adds an output of a random signal generator to both an input data signal and an output data signal. The descrambler modulo 2 adds an output of a second random signal generator to both an input data signal and an output data signal.Type: GrantFiled: April 1, 1985Date of Patent: January 27, 1987Assignee: NEC CorporationInventors: Goro Oshima, Kotaro Kato
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Patent number: 4530001Abstract: The semiconductor device comprises a semiconductor substrate, a plurality of spaced active elements, for example, of a planer type formed on one surface of the substrate, and a supporting plate bonded to the opposite surface of the substrate. A groove is cut through the substrate to reach the supporting plate for isolating the active elements.Type: GrantFiled: September 15, 1981Date of Patent: July 16, 1985Assignees: Oki Electric Industry Co., Ltd., Nippon Telegraph & Telephone Public Corp.Inventors: Haruo Mori, Yasuo Ohno, Yutaka Ohta, Hiroshi Tanabe, Kotaro Kato
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Patent number: 4489340Abstract: A PNPN semiconductor switch including an N type semiconductor substrate, spaced apart first and second P type diffused regions formed on a surface of an N type substrate, spaced apart first and second N type diffused regions formed in the second P type diffused region, a first gate insulating layer formed on the surface of the second P type diffused region between the first and second N type diffused regions to cover portions thereof, a first gate electrode formed on the first gate insulating layer between the first and second N type diffused regions, a resistance region disposed on the first gate insulating layer, one end of the resistance region on the side opposite to the first gate electrode, a second gate insulating layer overlying the first gate electrode and the resistance region, a semiinsulating layer formed on the surface of the substrate except over the first and second P type diffused regions, an insulating layer overlying the semiinsulating layer, a P gate electrode electrically connected to theType: GrantFiled: January 28, 1981Date of Patent: December 18, 1984Assignees: Nippon Telegraph & Telephone Public Corporation, Oki Electric Industry Co., Ltd.Inventors: Jun Ueda, Haruo Mori, Kazuo Hagimura, Hirokazu Tsukada, Kotaro Kato
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Patent number: 4393573Abstract: The semiconductor device is provided with semiconductor elements having the complementary characteristics and high breakdown strength. These semiconductor elements are formed in N and P islands respectively each having an inverted frustum shape.Surfaces of the frustum are inclined by an angle determined by semiconductor crystal structure. Side and bottom surfaces of the islands are formed adjacent to an insulating layer and both islands are supported part from the polycrystalline semiconductor layer. All side and bottom surfaces of the islands adjacent the insulating layer are made of high impurity substance of the same type as respective islands.Type: GrantFiled: August 26, 1980Date of Patent: July 19, 1983Assignee: Nippon Telegraph & Telephone Public CorporationInventors: Kotaro Kato, Tetsuma Sakurai
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Patent number: 4339817Abstract: A clock recovery circuit includes an oscillator having a frequency which is substantially equal to the clock frequency of bursts which are transmitted from a plurality of stations. A phase difference detector circuit responds to phase differences between clock signals extracted from each of the bursts and from the output from the oscillator. An averaging circuit averages the detected phase differences over an interval which is designated by a first control signal. A memory circuit stores the averaged phase difference in response to a second control signal and reads out the stored phase differences in response to a third control signal. A control circuit generates the first to third control signals in response to the output from the oscillator. A phase shift circuit shifts the phase of the output from the oscillator, based on the phase difference read out from the memory circuit. This generates and recovers the original clock pulse signal.Type: GrantFiled: September 2, 1980Date of Patent: July 13, 1982Assignees: Nippon Electric Co., Ltd., Nippon Telegraph & Telephone Public CorporationInventors: Masaharu Hata, Kotaro Kato
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Patent number: 4244000Abstract: A circuit for preventing a dV/dt erroneous operation of a PNPN semiconductor switch is replaced by a capacitance on the surface of a semiconductor substrate, a high resistance gate electrode. In other words, such a circuit is formed on the surface of the substrate by a slight modification of the basic design without decreasing the chip area and without isolating component elements.Type: GrantFiled: November 20, 1979Date of Patent: January 6, 1981Assignees: Nippon Telegraph and Telephone Public Corporation, Oki Electric Industry Company, Ltd.Inventors: Jun Ueda, Haruo Mori, Kazuo Hagimura, Kotaro Kato
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Patent number: 4210996Abstract: Current having a density higher than a critical value is passed through a polycrystalline resistor doped with impurities at a concentration higher than a critical value to decreasingly correct the initial value of the resistance, thereby trimming the resistance value of the resistor. When the resistor is used in a semiconductor integrated circuit, the current is passed through the existing (not additional) terminals of the integrated circuit.Type: GrantFiled: April 26, 1978Date of Patent: July 8, 1980Assignee: Nippon Telegraph and Telephone Public CorporationInventors: Yoshihito Amemiya, Kotaro Kato
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Patent number: 4004162Abstract: A clock signal reproducing network for PCM signal reception is capable of reproducing a clock signal even if the clock component is absent in the input digital signal for a prolonged period of time. The network includes a clock signal component extracting circuit and a bandpass filter for extracting and band-limiting the clock signal component in a received digital signal. An envelope detection circuit and a level decision circuit are connected to receive the output of the bandpass filter to provide a control signal to an output switching circuit. When the amplitude of the envelope of the filter output is high, the output of the bandpass filter is used directly as a reproduced clock signal. When the amplitude of the envelope is low, the clock signal obtained immediately before the filter amplitude becomes small is derived repeatedly from a delay circuit as a substituted clock signal.Type: GrantFiled: January 22, 1976Date of Patent: January 18, 1977Assignee: Nippon Electric Company, Ltd.Inventors: Kotaro Kato, Haruki Takai
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Patent number: 3962860Abstract: A quartz crystal timepiece incorporating a vibrator unit is disclosed. The vibrator unit is hermetically sealed in a case on which a condenser is fixed and the condenser compensates the oscillating frequency of said vibrator unit to a predetermined center frequency by suitably selecting the capacitance of the condenser after measuring the natural frequency of the vibrator unit. Then there is no need to adjust each vibrator unit to the predetermined center frequency during assembling process.Type: GrantFiled: August 30, 1974Date of Patent: June 15, 1976Assignee: Kabushiki Kaisha DainiInventors: Kotaro Kato, Makoto Morimoto