Patents by Inventor Kotaro Kihara

Kotaro Kihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8685854
    Abstract: A process for burying a tungsten member into a blind hole formed in a wafer, in which blind hole a through via is to be made. Film-formation (for forming the tungsten member) is carried out to position, at the periphery of the wafer, the outer circumference of the tungsten member inside the outer circumference of a barrier metal beneath the tungsten film. This process makes it possible to bury the tungsten member, which may be relatively thin, into the blind hole, which may be relatively large, so as to decrease a warp of the wafer and further prevent an underlying layer beneath the tungsten member from being peeled at the periphery of the wafer.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: April 1, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuhito Ichinose, Kotaro Kihara, Tatsunori Murata
  • Patent number: 8338247
    Abstract: To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: December 25, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tadashi Yamaguchi, Toshiaki Tsutsumi, Satoshi Ogino, Kazumasa Yonekura, Kenji Kawai, Yoshihiro Miyagawa, Tomonori Okudaira, Keiichiro Kashihara, Kotaro Kihara
  • Publication number: 20110221063
    Abstract: A process for burying a tungsten member into a blind hole formed in a wafer, in which blind hole a through via is to be made. Film-formation (for forming the tungsten member) is carried out to position, at the periphery of the wafer, the outer circumference of the tungsten member inside the outer circumference of a barrier metal beneath the tungsten film. This process makes it possible to bury the tungsten member, which may be relatively thin, into the blind hole, which may be relatively large, so as to decrease a warp of the wafer and further prevent an underlying layer beneath the tungsten member from being peeled at the periphery of the wafer.
    Type: Application
    Filed: March 11, 2011
    Publication date: September 15, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Kazuhito Ichinose, Kotaro Kihara, Tatsunori Murata
  • Publication number: 20110037103
    Abstract: To improve performance of a semiconductor device. Over a semiconductor substrate, a plurality of p-channel type MISFETs for logic, a plurality of n-channel type MISFETs for logic, a plurality of p-channel type MISFETs for memory, and a plurality of n-channel type MISFETs for memory are mixedly mounted. At least a part of the p-channel type MISFETs for logic have each a source/drain region constituted by silicon-germanium, and all the n-channel type MISFETs for logic have each a source/drain region constituted by silicon. All the p-channel type MISFETs for memory have each a source/drain region constituted by silicon, and all the n-channel type MISFETs for memory have each a source/drain region constituted by silicon.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 17, 2011
    Inventors: Tadashi YAMAGUCHI, Keiichiro KASHIHARA, Toshiaki TSUTSUMI, Tomonori OKUDAIRA, Kotaro KIHARA
  • Publication number: 20100230761
    Abstract: To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.
    Type: Application
    Filed: March 9, 2010
    Publication date: September 16, 2010
    Inventors: Tadashi Yamaguchi, Toshiaki Tsutsumi, Satoshi Ogino, Kazumasa Yonekura, Kenji Kawai, Yoshihiro Miyagawa, Tomonori Okudaira, Keiichiro Kashihara, Kotaro Kihara