Patents by Inventor Kotaro Kodani

Kotaro Kodani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10177012
    Abstract: A wiring substrate includes a first insulation layer having a component mounting area and a mark formation area, an electrode pad arranged in the component mounting area and having an upper surface exposed from the first insulation layer and a side surface and a lower surface embedded in the first insulation layer, and a mark arranged in the mark formation area and formed of an insulation pattern layer having an upper surface exposed from the first insulation layer and a side surface and a lower surface embedded in the first insulation layer. A color of the first insulation layer and a color of the insulation pattern layer are different.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: January 8, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kotaro Kodani
  • Patent number: 10117336
    Abstract: A wiring substrate includes an insulating layer, a connection pad buried in the insulating layer in a state that an upper surface of the connection pad is exposed from an upper surface of the insulating layer and a lower surface and at least a part of a side surface of the connection pad contact the insulating layer, and a concave level difference portion formed in the insulating layer around an outer periphery part of the connection pad, wherein an upper surface of the connection pad and an upper surface of the insulating layer are arranged at a same height.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: October 30, 2018
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kentaro Kaneko, Toshimitsu Omiya, Kotaro Kodani, Junichi Nakamura, Kazuhiro Kobayashi
  • Publication number: 20180114702
    Abstract: A wiring substrate includes a first insulation layer having a component mounting area and a mark formation area, an electrode pad arranged in the component mounting area and having an upper surface exposed from the first insulation layer and a side surface and a lower surface embedded in the first insulation layer, and a mark arranged in the mark formation area and formed of an insulation pattern layer having an upper surface exposed from the first insulation layer and a side surface and a lower surface embedded in the first insulation layer. A color of the first insulation layer and a color of the insulation pattern layer are different.
    Type: Application
    Filed: October 20, 2017
    Publication date: April 26, 2018
    Inventor: Kotaro Kodani
  • Patent number: 9818702
    Abstract: A wiring substrate includes a first reinforcement pattern stacked on a lower surface of a first insulation layer at a peripheral region located at an outer side of a wiring formation region. A first reinforcement via extends through a second insulation layer in the thickness-wise direction and contacts the first reinforcement pattern. A second reinforcement pattern is stacked on a lower surface of the second insulation layer and connected to the first reinforcement pattern by the first reinforcement via. The first reinforcement via includes a top that partially extends into the first insulation layer.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: November 14, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES, CO., LTD.
    Inventor: Kotaro Kodani
  • Publication number: 20160379938
    Abstract: A wiring substrate includes a first reinforcement pattern stacked on a lower surface of a first insulation layer at a peripheral region located at an outer side of a wiring formation region. A first reinforcement via extends through a second insulation layer in the thickness-wise direction and contacts the first reinforcement pattern. A second reinforcement pattern is stacked on a lower surface of the second insulation layer and connected to the first reinforcement pattern by the first reinforcement via. The first reinforcement via includes a top that partially extends into the first insulation layer.
    Type: Application
    Filed: June 15, 2016
    Publication date: December 29, 2016
    Inventor: KOTARO KODANI
  • Patent number: 9345143
    Abstract: A wiring board includes an electrode pad having a first surface and a second surface located on an opposite side from the first surface, a conductor pattern connected to the first surface of the electrode pad, and an insulator layer embedded with the electrode pad and the conductor pattern. The insulator layer covers an outer peripheral portion of the second surface of the electrode pad.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: May 17, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kotaro Kodani, Kentaro Kaneko, Kazuhiro Kobayashi
  • Publication number: 20160044792
    Abstract: A wiring substrate includes an insulating layer, a connection pad buried in the insulating layer in a state that an upper surface of the connection pad is exposed from an upper surface of the insulating layer and a lower surface and at least a part of a side surface of the connection pad contact the insulating layer, and a concave level difference portion formed in the insulating layer around an outer periphery part of the connection pad, wherein an upper surface of the connection pad and an upper surface of the insulating layer are arranged at a same height.
    Type: Application
    Filed: October 26, 2015
    Publication date: February 11, 2016
    Applicant: Shinko Electric Industries Co., Ltd.
    Inventors: Kentaro KANEKO, Toshimitsu Omiya, Kotaro Kodani, Junichi Nakamura, Kazuhiro Kobayashi
  • Patent number: 9257373
    Abstract: A wiring board includes a wiring forming region in which a plurality of wiring layers are stacked while sandwiching insulating layers, an outer periphery region which is arranged around the wiring forming region and in which a reinforcing pattern is formed in the same layer as each of the wiring layers. An area ratio of the reinforcing pattern to the outer periphery region and an area ratio of the wiring layer to the wiring forming region are substantially the same in each of the layers, and the reinforcing patterns exist without a gap in the outer periphery region when the wiring board is viewed in planar perspective.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: February 9, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Junichi Nakamura, Kotaro Kodani, Michiro Ogawa
  • Patent number: 9247644
    Abstract: A wiring substrate includes an insulating layer, a pad, and a solder resist layer. The insulating layer has a first surface formed with a first recess portion. The pad is embedded in the first recess portion. The pad includes a second surface and a third surface. The third surface that is located at a lower position than the first surface so as to expose an inner wall surface of the first recess portion. The pad is formed with a second recess portion in a center portion of the third surface. The solder resist layer is provided on the first surface. An adjacent portion of the first surface to a peripheral portion of the first recess portion is smaller in roughness than a region of the first surface peripheral to the adjacent portion of the first surface.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: January 26, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kentaro Kaneko, Kazuhiro Kobayashi, Toshimitsu Omiya, Kotaro Kodani, Shunichiro Matsumoto, Ruofan Tang
  • Patent number: 9210808
    Abstract: A wiring substrate includes an insulating layer, a connection pad buried in the insulating layer in a state that an upper surface of the connection pad is exposed from an upper surface of the insulating layer and a lower surface and at least a part of a side surface of the connection pad contact the insulating layer, and a concave level difference portion formed in the insulating layer around an outer periphery part of the connection pad, wherein an upper surface of the connection pad and an upper surface of the insulating layer are arranged at a same height.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 8, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kentaro Kaneko, Toshimitsu Omiya, Kotaro Kodani, Junichi Nakamura, Kazuhiro Kobayashi
  • Publication number: 20150289380
    Abstract: A wiring board includes an electrode pad having a first surface and a second surface located on an opposite side from the first surface, a conductor pattern connected to the first surface of the electrode pad, and an insulator layer embedded with the electrode pad and the conductor pattern. The insulator layer covers an outer peripheral portion of the second surface of the electrode pad.
    Type: Application
    Filed: June 17, 2015
    Publication date: October 8, 2015
    Inventors: Kotaro KODANI, Kentaro KANEKO, Kazuhiro KOBAYASHI
  • Patent number: 9137896
    Abstract: A wiring substrate includes a first insulating layer, an adhesion insulating layer formed under the first insulating layer and an outer face of the adhesion insulating layer is made to a roughened face, a first wiring layer formed on the first insulating layer, a second insulating layer formed on the first insulating layer, and in which a first via hole reaching the first wiring layer is provided, a second wiring layer formed on the second insulating layer, and connected to the first wiring layer through the first via hole, a second via hole formed in the adhesion insulating layer and the first insulating layer, and reaching the first wiring layer, and a third wiring layer formed on the outer face of the adhesion insulating layer, and connected to the first wiring layer through the second via hole.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: September 15, 2015
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kazuhiro Kobayashi, Kotaro Kodani, Junichi Nakamura, Kentaro Kaneko
  • Publication number: 20150206833
    Abstract: A method of making a wiring substrate includes forming a first metal layer on a surface of a support member, the first metal layer having at least one columnar through hole that exposes the surface of the support member, forming a columnar metal layer that fills the columnar through hole, forming an insulating layer on the columnar metal layer and on the first metal layer, forming an interconnection layer on a first surface of the insulating layer such that the interconnection layer is electrically connected to the columnar metal layer through the insulating layer, and forming a protruding part including at least part of the columnar metal layer by removing at least the support member and the first metal layer, the protruding part protruding from a second surface of the insulating layer opposite the first surface and serving as at least part of a connection terminal of the wiring substrate.
    Type: Application
    Filed: March 31, 2015
    Publication date: July 23, 2015
    Inventors: Kotaro KODANI, Junichi NAKAMURA
  • Patent number: 9089041
    Abstract: A wiring board includes an electrode pad having a first surface and a second surface located on an opposite side from the first surface, a conductor pattern connected to the first surface of the electrode pad, and an insulator layer embedded with the electrode pad and the conductor pattern. The insulator layer covers an outer peripheral portion of the second surface of the electrode pad.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: July 21, 2015
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kotaro Kodani, Kentaro Kaneko, Kazuhiro Kobayashi
  • Patent number: 9018538
    Abstract: A method of making a wiring substrate includes forming a first metal layer on a surface of a support member, the first metal layer having at least one columnar through hole that exposes the surface of the support member, forming a columnar metal layer that fills the columnar through hole, forming an insulating layer on the columnar metal layer and on the first metal layer, forming an interconnection layer on a first surface of the insulating layer such that the interconnection layer is electrically connected to the columnar metal layer through the insulating layer, and forming a protruding part including at least part of the columnar metal layer by removing at least the support member and the first metal layer, the protruding part protruding from a second surface of the insulating layer opposite the first surface and serving as at least part of a connection terminal of the wiring substrate.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: April 28, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kotaro Kodani, Junichi Nakamura
  • Patent number: 9006103
    Abstract: A method of manufacturing a wiring substrate, includes, forming an etching stop layer and a first wiring layer on a supporting member, forming a first insulating layer on the first wiring layer, forming a via hole reaching the first wiring layer, and forming the wiring layers of an n-layer and the insulating layers of an n-layer, removing the supporting member and the etching stop layer, thereby forming a build-up intermediate body, forming a second insulating layer on the wiring layer of an n-th layer, and forming a third insulating layer on first wiring layer, forming a via hole reaching the wiring layer of the n-th layer, and forming a via hole reaching the first wiring layer, forming a roughened face to the third insulating layer, and forming a second wiring layer connected to the wiring layer, and forming a third wiring layer connected to the first wiring layer.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: April 14, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kazuhiro Kobayashi, Kotaro Kodani, Junichi Nakamura, Kentaro Kaneko
  • Publication number: 20150014027
    Abstract: A wiring substrate includes an insulating layer, a pad, and a solder resist layer. The insulating layer has a first surface formed with a first recess portion. The pad is embedded in the first recess portion. The pad includes a second surface and a third surface. The third surface that is located at a lower position than the first surface so as to expose an inner wall surface of the first recess portion. The pad is formed with a second recess portion in a center portion of the third surface. The solder resist layer is provided on the first surface. An adjacent portion of the first surface to a peripheral portion of the first recess portion is smaller in roughness than a region of the first surface peripheral to the adjacent portion of the first surface.
    Type: Application
    Filed: July 11, 2014
    Publication date: January 15, 2015
    Inventors: Kentaro Kaneko, Kazuhiro Kobayashi, Toshimitsu Omiya, Kotaro Kodani, Shunichiro Matsumoto, Ruofan Tang
  • Patent number: 8797757
    Abstract: A wiring substrate includes plural insulating layers including an outermost insulating layer; and plural wiring layers which are alternately laminated between the insulating layers and include outermost wiring layers exposed from the outermost insulating layer and through wirings having electrode pads on end portions of the through wirings and penetrating through the outermost insulating layer, wherein the electrode pads of the through wirings are exposed from the outermost insulating layer, and a part of the outermost wiring layers overlaps the end portions of the through wirings and is connected to the through wirings.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: August 5, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kentaro Kaneko, Toshiaki Aoki, Kazuhiro Kobayashi, Kotaro Kodani, Junichi Nakamura
  • Patent number: 8790504
    Abstract: There is provided a method of manufacturing a wiring substrate. The method includes: (a) forming a first resist layer having first openings therein on a first surface of a support plate, forming first plated films in the first openings by an electrolytic plating method, and removing the first resist layer; (b) forming a second resist layer having second openings therein on the first surface of the support plate, forming second plated films in the second openings by an electrolytic plating method, and removing the second resist layer; (c) forming a wiring layer and an insulating layer such that the wiring layer is electrically connected to the first and second plated films; and (d) removing the support plate to expose the first and second plated films.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: July 29, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Kotaro Kodani
  • Patent number: 8760883
    Abstract: A wiring substrate includes plural insulating layers including an outermost insulating layer; and plural wiring layers which are alternately laminated between the insulating layers and include outermost wiring layers exposed from the outermost insulating layer and through wirings having electrode pads on end portions of the through wirings and penetrating through the outermost insulating layer, wherein the electrode pads of the through wirings are exposed from the outermost insulating layer, and a part of the outermost wiring layers overlaps the end portions of the through wirings and is connected to the through wirings.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: June 24, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kentaro Kaneko, Toshiaki Aoki, Kazuhiro Kobayashi, Kotaro Kodani, Junichi Nakamura