Patents by Inventor Kotaro Nishimura
Kotaro Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120359Abstract: The present disclosure relates to a photodetection device and an electronic apparatus that allow for reducing surface reflection from an on-chip microlens and suppressing deterioration of image quality. Provided is a photodetection device including: a plurality of pixels that have photoelectric conversion units; on-chip microlenses that are formed in such a way as to correspond to the individual pixels; and an antireflection film that is formed on a surface of the on-chip microlens, in which the antireflection film is constituted by a stacking of: a first inorganic film that is formed by a metal oxide film; and a second inorganic film that is formed on a surface of the first inorganic film and has a lower refractive index than the first inorganic film. The present disclosure can be applied to, for example, a CMOS solid-state imaging device.Type: ApplicationFiled: February 21, 2022Publication date: April 11, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yusuke MORIYA, Atsushi YAMAMOTO, Tomiyuki YUKAWA, Kotaro NISHIMURA, Shigehiro IKEHARA, Shogo OTANI, Hiroshi KATO
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Publication number: 20220130880Abstract: The present disclosure relates to a camera package, a method for manufacturing a camera package, and an electronic device with which it is possible to reduce manufacturing cost for lens formation. The camera package according to the present disclosure includes: a solid-state imaging element; and a lens formed above a transparent substrate that protects the solid-state imaging element. A lens formation region in which the lens is formed above the transparent substrate and a lens free region around the lens formation region differ in contact angle. The present disclosure can be applied to, for example, a camera package in which a lens is disposed above a solid-state imaging element, or the like.Type: ApplicationFiled: February 18, 2020Publication date: April 28, 2022Inventors: HIROYASU MATSUGAI, KOTARO NISHIMURA
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Publication number: 20210223512Abstract: The present disclosure relates to an imaging device capable of achieving miniaturization and height reduction of a device configuration, reducing generation of a flare or a ghost, and preventing separation of a lens. Side surfaces of a lens provided on a solid-state imaging element form a multistep shape. Angles formed by the side surfaces forming the multistep shape with respect to an incident direction of incident light differ from each other. The present disclosure is applicable to an imaging device.Type: ApplicationFiled: May 24, 2019Publication date: July 22, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Kotaro NISHIMURA, Atsushi YAMAMOTO, Yoshinori TOUMIYA
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Patent number: 5446689Abstract: A semiconductor memory device is provided which has a plurality of memory cells each including a pair of cross-coupled metal insulated gate field effect transistors having channels of N-conductivity type, and a pair of load resistors of polycrystalline silicon respectively coupled to the pair of cross-coupled transistors. A peripheral circuit is also provided which is constituted by metal insulated gate field effect transistors having channels of the N-conductivity type and metal insulated gate field effect transistors having channels of P-conductivity type. The semiconductor memory device is formed in an N-type semiconductor substrate, and the pair of cross-coupled metal insulated gate field effect transistors of the memory cells are formed in a well region of P-type which forms a PN-junction with the semiconductor substrate to help reduce the susceptibility to soft errors.Type: GrantFiled: April 21, 1994Date of Patent: August 29, 1995Assignee: Hitachi, Ltd.Inventors: Tokumasa Yasui, Shinji Shimizu, Kotaro Nishimura
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Patent number: 5359562Abstract: A semiconductor memory device is provided which has a plurality of memory cells each including a pair of cross-coupled metal insulated gate field effect transistors having channels of N-conductivity type, and a pair of load resistors of polycrystalline silicon respectively coupled to the pair of cross-coupled transistors. A peripheral circuit is also provided which is constituted by metal insulated gate field effect transistors having channels of the N-conductivity type and metal insulated gate field effect transistors having channels of P-conductivity type. The semiconductor memory device is formed in an N-type semiconductor substrate, and the pair of cross-coupled metal insulated gate field effect transistors of the memory cells are formed in a well region of P-type which forms a PN-junction with the semiconductor substrate to help reduce the susceptibility to soft errors.Type: GrantFiled: April 15, 1991Date of Patent: October 25, 1994Assignee: Hitachi, Ltd.Inventors: Tokumasa Yasui, Shinji Shimizu, Kotaro Nishimura
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Patent number: 5159260Abstract: This reference voltage generator device detects a voltage corresponding to an energy gap of a semiconductor, or a voltage of a value close thereto, or a voltage based on an energy level of a semiconductor, and generates the detected voltage as a reference voltage. The reference voltage is generated by detecting a difference of threshold voltages of first and second insulated gate field-effect transistors (IGFETs). Gate electrodes of the first and second IGFETs are formed on gate insulating films which are formed on different surface areas of an identical semiconductor substrate under substantially the same conditions. The gate electrodes of the first and second IGFETs are respectively made of two semiconductors which are selected from among a semiconductor of a first conductivity type, a semiconductor of a second conductivity type and an intrinsic semiconductor made of an identical semiconductor material, and which have Fermi energy levels of values different from each other.Type: GrantFiled: January 7, 1987Date of Patent: October 27, 1992Assignee: Hitachi, Ltd.Inventors: Kanji Yoh, Osamu Yamashiro, Satoshi Meguro, Koichi Nagasawa, Kotaro Nishimura, Harumi Wakimoto, Kazutaka Narita
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Patent number: 5087956Abstract: An SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into at least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.Type: GrantFiled: May 30, 1989Date of Patent: February 11, 1992Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Satoshi Meguro, Kotaro Nishimura, Sho Yamamoto, Nobuyoshi Tanimura
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Patent number: 4841481Abstract: An SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into a least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.Type: GrantFiled: July 28, 1988Date of Patent: June 20, 1989Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Satoshi Meguro, Kotaro Nishimura, Sho Yamamoto, Nobuyoshi Tanimura
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Patent number: 4774203Abstract: A method of making a static random-access memory device or SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into at least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.Type: GrantFiled: August 22, 1986Date of Patent: September 27, 1988Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Satoshi Meguro, Kotaro Nishimura, Sho Yamamoto, Nobuyoshi Tanimura
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Patent number: 4641285Abstract: The line change-over circuit suitable for the semiconductor memory having a redundancy memory column comprises a pair of transfer gate elements provided between a first node to which a first signal to be transmitted is supplied and a pair of transmission lines, first and second switch elements. The paired transfer gate elements are controlled on a switch in complementary manner each other according to a transfer signal. The first switch element is controlled on a switch according to the transfer signal, and the second switch element is controlled on a switch according to the first signal transmitted to one of the paired transmission lines. The first switch element turns one of the transmission lines to a fixed potential like ground potential when it is kept on, and the second switch element turns the other of the transmission lines to a fixed potential when it is kept on. The line change-over circuit in the above configuration is effective to prevent a floating state of the paired transmission lines.Type: GrantFiled: August 13, 1984Date of Patent: February 3, 1987Assignee: Hitachi, Ltd.Inventors: Yukio Sasaki, Kotaro Nishimura, Osamu Minato
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Patent number: 4458348Abstract: An electrically programmable read only memory includes a plurality of non-volatile memory elements having control gates which are commonly connected to a first word line and drains which are coupled to a write-down circuit for supplying a write-down voltage to said drains. To prevent the flow of leakage current caused by parasitic capacitance, at least one of source electrodes of the plurality of non-volatile memory elements is connected to ground potential through the drain-source path of a first switch MISFET whose gate electrode is connected to the first word line. When a word line driving signal of non-selection level is applied to the first word line, the first switch MISFET is non-conductive. Thus, leakage current is prohibited from flowing through the first switch MISFET.Type: GrantFiled: May 21, 1982Date of Patent: July 3, 1984Assignee: Hitachi, Ltd.Inventors: Minoru Fukuda, Shigeru Yamatani, Kotaro Nishimura, Akira Endo
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Patent number: 4300213Abstract: Digit lines, connected to the input and output terminals of a memory cell composed of MISFETs, are coupled to common data lines through a switching circuit which is controlled by a decoder circuit. There is also connected with the digit lines a load which is composed of a plurality of enhancement mode MISFETs connected in series in the diode form. The high level of the signals at the digit lines is lowered by the action of the load means. In response to the reduction in the potentials at the digit lines, the switching means is rendered conductive at an early rise time of control signals. As a result, the operating speed of the memory circuit can be increased.Type: GrantFiled: October 31, 1979Date of Patent: November 10, 1981Assignees: Hitachi, Ltd., Hitachi Ome Electronic Co., Ltd.Inventors: Nobuyoshi Tanimura, Hiroshi Fukuta, Kotaro Nishimura, Tokumasa Yasui
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Patent number: 4261004Abstract: On the surface of an insulating film formed on the surface of a semiconductor substrate on which an MOS type semiconductor device to be protected is formed, there are formed a first polycrystal silicon member having input and output terminals and a resistivity lower than 1 K.OMEGA./.quadrature. and a second polycrystalline silicon member having a resistivity lower than 1 K.OMEGA./.quadrature. and being maintained at a fixed potential. This second polycrystalline silicon member faces at least a part of the first silicon member with polycrystalline silicon of a resistivity higher than 100 K.OMEGA./.quadrature. interposed therebetween. The input terminal of the first polycrystalline silicon member is connected to an input pad of the MOS type semiconductor device to be protected and the output terminal of the first polycrystalline silicon member is connected to an input gate of the semiconductor device to be protected.Type: GrantFiled: August 1, 1978Date of Patent: April 7, 1981Assignee: Hitachi, Ltd.Inventors: Toshiaki Masuhara, Osamu Minato, Yoshio Sakai, Toshio Sasaki, Masaharu Kubo, Kotaro Nishimura, Tokumasa Yasui
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Patent number: 4063118Abstract: In a multiplicity of NAND decoders, each comprises a dynamic ratioless circuit including a capacitor to be charged in response to a precharge pulse, an MOS logic circuit for discharging the capacitor by an address pulse in the non-selection mode, and first and second MOSFETs connected in series between a clock pulse terminal and ground. The first MOSFET conducts in response to the terminal voltage of the capacitor to transmit a clock pulse from its drain and supplies an output to a word line. The terminal voltage of the capacitor in one decoder is applied to the gate of the second MOSFET of another decoder and the word line output of the other decoder is grounded even during the discharging period of the capacitor in the non-selection mode of the other decoder, enabling a synchronous supply of the address and the clock pulses.Type: GrantFiled: May 25, 1976Date of Patent: December 13, 1977Assignee: Hitachi, Ltd.Inventor: Kotaro Nishimura
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Patent number: 4060740Abstract: In a sensing amplifier for a capacitive MISFET memory, the level of an output signal from the memory is shifted by a signal level shifting circuit and the level-shifted signal is applied to an input of the sensing amplifier to thereby provide a high speed operation.Type: GrantFiled: May 12, 1976Date of Patent: November 29, 1977Assignee: Hitachi, Ltd.Inventor: Kotaro Nishimura