Patents by Inventor Kothandan Shanmugam

Kothandan Shanmugam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11085950
    Abstract: In one embodiment, the present invention includes an interface assembly for a vertical probe contactor. The interface assembly comprises a base board, a mounting board, a depth adjust plate, and an interface apparatus. The depth adjust plate is between the base board and the mounting board, and the interface apparatus is mounted to the mounting board. The interface apparatus is configured to receive the vertical probe contactor through an opening in the base board and a corresponding opening in the depth adjust plate. A thickness of the depth adjust plate defines a vertical distance between a wafer side of the base board and a plurality of probe tips of the vertical probe contactor.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: August 10, 2021
    Assignee: Spire Manufacturing
    Inventors: Hai Dau, Lim Hooi Weng, Kothandan Shanmugam, Christine Bui
  • Publication number: 20190257858
    Abstract: In one embodiment, the present invention includes an interface assembly for a vertical probe contactor. The interface assembly comprises a base board, a mounting board, a depth adjust plate, and an interface apparatus. The depth adjust plate is between the base board and the mounting board, and the interface apparatus is mounted to the mounting board. The interface apparatus is configured to receive the vertical probe contactor through an opening in the base board and a corresponding opening in the depth adjust plate. A thickness of the depth adjust plate defines a vertical distance between a wafer side of the base board and a plurality of probe tips of the vertical probe contactor.
    Type: Application
    Filed: December 18, 2018
    Publication date: August 22, 2019
    Inventors: Hai Dau, Lim Hooi Weng, Kothandan Shanmugam, Christine Bui
  • Patent number: 10096958
    Abstract: In one embodiment, the present invention includes an interface apparatus for semiconductor testing. The interface apparatus includes a housing. The housing includes a lower housing substrate and an upper housing substrate. The lower housing substrate has a plurality of apertures arranged according to a fine pitch, and the upper housing substrate has a plurality of apertures arranged according to a coarse pitch. A plurality of wires passes through the plurality of apertures from the lower housing substrate to the upper housing substrate. Each wire has plated conductive ends emanating from opposing sides of the housing. The plurality of apertures of the lower housing substrate corresponds to the plurality of apertures of the upper housing substrate. The interface apparatus transforms a pattern having a course pitch to a pattern having a fine pitch.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: October 9, 2018
    Assignee: Spire Manufacturing Inc.
    Inventors: Hai Dau, Lim Hooi Weng, Kothandan Shanmugam, Christine Bui
  • Patent number: 9933479
    Abstract: The present invention includes an interface apparatus for semiconductor testing. The interface apparatus comprises a housing substrate and two product substrates. The first product substrate has a first micro-scale conductive pattern and is situated within a first opening of the housing substrate. The second product substrate has a second micro-scale conductive pattern and is situated within a second opening of the housing substrate. The first and the second micro-scale conductive patterns are aligned to a conductive semiconductor wafer pattern using a continuous translucent media having targets corresponding to the conductive semiconductor wafer pattern.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: April 3, 2018
    Assignee: Spire Manufacturing
    Inventors: Hai Dau, Lim Hooi Weng, Kothandan Shanmugam, Christine Bui
  • Publication number: 20170131348
    Abstract: In one embodiment, the present invention includes an interface apparatus for semiconductor testing. The interface apparatus comprises a housing substrate and two product substrates. The first product substrate has a first micro-scale conductive pattern and is situated within a first opening of the housing substrate. The second product substrate has a second micro-scale conductive pattern and is situated within a second opening of the housing substrate. The first and the second micro-scale conductive patterns are aligned to a conductive semiconductor wafer pattern using a continuous translucent media having targets corresponding to the conductive semiconductor wafer pattern.
    Type: Application
    Filed: November 11, 2015
    Publication date: May 11, 2017
    Inventors: Hai Dau, Lim Hooi Weng, Kothandan Shanmugam, Christine Bui
  • Publication number: 20170093101
    Abstract: In one embodiment, the present invention includes an interface apparatus for semiconductor testing. The interface apparatus includes a housing. The housing includes a lower housing substrate and an upper housing substrate. The lower housing substrate has a plurality of apertures arranged according to a fine pitch, and the upper housing substrate has a plurality of apertures arranged according to a coarse pitch. A plurality of wires passes through the plurality of apertures from the lower housing substrate to the upper housing substrate. Each wire has plated conductive ends emanating from opposing sides of the housing. The plurality of apertures of the lower housing substrate corresponds to the plurality of apertures of the upper housing substrate. The interface apparatus transforms a pattern having a course pitch to a pattern having a fine pitch.
    Type: Application
    Filed: September 24, 2015
    Publication date: March 30, 2017
    Inventors: Hai Dau, Lim Hooi Weng, Kothandan Shanmugam, Christine Bui