Abstract: A Bi-CMOS circuit includes a first bipolar, a second bipolar transistor and a CMOS control unit for performing switching controls of the first and second bipolar transistors on the basis of an input signal applied to an input terminal and for controlling an output signal output via the output terminal on the basis of the input signal. A turn-OFF unit temporality couples the base of the first bipolar transistor to a low-potential side power supply line on the basis of a current flowing in said control means when the first bipolar transistor is turned OFF, so that the first bipolar transistor can be rapidly turned OFF.

Abstract: A semiconductor integrated circuit device includes a preceding circuit portion, a flip-flop circuit portion receiving complementary output signals of the preceding circuit portion, for latching data in accordance with the complementary output signals of the preceding circuit portion, and a compensation circuit portion receiving complementary output signals of the flip-flop circuit portion and receiving the complementary output signals of the preceding circuit portion without passing through the flip-flop circuit portion, for compensating driving power and decreasing a delay time of a specific phase. Therefore, the delay time of the semiconductor integrated circuit device can be decreased in one phase (specific phase).

Abstract: A Bi-CMOS logic circuit includes first and second bipolar transistors connected in series between a first power source and a second power source. An output signal is drawn from a connection node at which first and second bipolar transistors are connected in series. The Bi-CMOS logic circuit also includes a first impedance element, connected between a base and an emitter of the first bipolar transistor, providing a first impedance, and a second impedance element, connected between a base of the second bipolar transistor and an emitter thereof, providing a second impedance.

Abstract: A Bi-CMOS logic circuit includes a Bi-CMOS circuit which is composed of first and second bipolar transistors, first and second resistors, and first and second MOS transistors. An input signal is applied to the gates of the first and second MOS transistors, and an output signal is drawn from a connection node at which the first and second bipolar transistors are connected in series between first and second power sources. A third MOS transistor is connected between the collector and emitter of the first bipolar transistor. The input signal is applied to the gate of the third MOS transistor. In place of or in addition to the third MOS transistor, a fourth MOS transistor is provided which is connected between the collector and emitter of the second bipolar transistor. The third and fourth MOS transistors function to decrease roundings of rising and falling edges of the waveform of the output signal.