Patents by Inventor Kou-Ning Chiang

Kou-Ning Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7884464
    Abstract: The present invention provides a 3D electronic packaging unit having a conductive supporting substrate that can achieve multi-chip stacking through the signal contacts on the both sides of the unit. The packaging unit can be batched manufactured on wafers or substrates, and thus reduce the manufacturing cost of each individual packaging unit; moreover, the conductive supporting substrate can be utilized to provide signal transmission of the electronic elements, and the supporting substrate can be used as a ground terminal for the carried electronic elements to enhance electric performance of the electronic elements. The supporting substrate is also a good thermal conductor that can release effectively heat energy generated by the electronic elements and accumulated inside the package to the outside of the package along the substrate to enhance reliability of the packaging structure.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: February 8, 2011
    Assignee: Advanced Chip Engineering Technologies Inc.
    Inventors: Ming-Chih Yew, Chang-Ann Yuan, Chan-Yen Chou, Kou-Ning Chiang
  • Publication number: 20080142941
    Abstract: The present invention proposes a 3D electronic packaging structure with enhanced grounding performance and embedded antenna, and the packaging unit can achieve multi-chip stacking through the signal contacts on the top and bottom surfaces of the unit. A single or multiple grounding layers are on the back of the substrate in the packaging unit to facilitate the grounding for the semiconductor element; further, the packaging unit is applicable to a wafer level packaging process, so the manufacturing cost of each individual packaging unit is reduced. The above grounding layers are also the signal transmission paths of the electronic elements in the packaging structure of the invention, and a single or multiple via holes around the electronic element layers allow electrical signal connection between the top and bottom surfaces of the packaging structure, and thus enable more functionality in the packaging unit.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 19, 2008
    Inventors: Ming-Chih Yew, Chien-Chia Chiu, Kou-Ning Chiang, Wen-Kun Yang
  • Publication number: 20070296065
    Abstract: The present invention provides a 3D electronic packaging unit having a conductive supporting substrate that can achieve multi-chip stacking through the signal contacts on the both sides of the unit. The packaging unit can be batched manufactured on wafers or substrates, and thus reduce the manufacturing cost of each individual packaging unit; moreover, the conductive supporting substrate can be utilized to provide signal transmission of the electronic elements, and the supporting substrate can be used as a ground terminal for the carried electronic elements to enhance electric performance of the electronic elements. The supporting substrate is also a good thermal conductor that can release effectively heat energy generated by the electronic elements and accumulated inside the package to the outside of the package along the substrate to enhance reliability of the packaging structure.
    Type: Application
    Filed: June 27, 2006
    Publication date: December 27, 2007
    Applicant: Advanced Chip Engineering Technology Inc.
    Inventors: Ming-Chih Yew, Chang-Ann Yuan, Chan-Yen Chou, Kou-Ning Chiang