Patents by Inventor Kou Tei
Kou Tei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11881266Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings. The memory cells are configured to retain a threshold voltage. The rows include full circle rows and semi-circle rows in which the memory holes are partially cut by a slit half etch. The memory holes of the semi-circle rows are coupled semi-circle bit lines and the memory holes of the full circle rows are coupled to full circle bit lines. A control means is configured to erase the memory cells in an erase operation. During the erase operation, the control means creates a capacitive coupling between each of the semi-circle bit lines and at least one neighboring one of the full circle bit lines to increase a semi-circle erase voltage applied to each of the semi-circle bit lines.Type: GrantFiled: February 8, 2022Date of Patent: January 23, 2024Assignee: SanDisk Technologies LLCInventors: Xiang Yang, Kou Tei, Ohwon Kwon
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Patent number: 11798638Abstract: Technology for mitigating interference to select transistors in 3D memory is disclosed. In one aspect, a control circuit pre-charges a first set of bit lines to a first voltage and pre-charges a second set of bit lines to a second voltage greater than the first voltage. The control circuit may increase the voltage on the first set of bit lines to the second voltage while the second set of bit lines are floating to couple up the voltages on the second set of bit lines to a voltage greater than the second voltage. The higher voltage on the second set of bit lines compensates for interference that some of the select transistors may experience from an adjacent select line. For example, the higher voltage can prevent a leakage current in the select transistors from occurring. Preventing the leakage current can improve boosting of NAND channel voltages, thereby preventing program disturb.Type: GrantFiled: September 24, 2021Date of Patent: October 24, 2023Assignee: SanDisk Technologies LLCInventors: Xiang Yang, Kou Tei, Ohwon Kwon
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Publication number: 20230326530Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in memory holes and grouped into a plurality of tiers. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states to store one bit as single-level cells and a plurality of bits as multi-level cells. The apparatus also includes a control means coupled to the word lines and the memory holes and configured to select a predetermined strobe quantity of the plurality of tiers of the memory cells separately for the memory cells operating as the single-level cells and the memory cells operating as the multi-level cells. The control means is also configured to trigger sensing of the predetermined strobe quantity of the plurality of tiers of the memory cells during a verify operation.Type: ApplicationFiled: April 7, 2022Publication date: October 12, 2023Applicant: SanDisk Technologies LLCInventors: Chin-Yi Chen, Muhammad Masuduzzaman, Kou Tei, Deepanshu Dutta, Hiroyuki Mizukoshi, Jiahui Yuan, Xiang Yang
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Publication number: 20230326531Abstract: Technology is disclosed herein for a memory system having a dynamic supply voltage to sense amplifiers. In an aspect, the supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.Type: ApplicationFiled: April 11, 2022Publication date: October 12, 2023Applicant: SanDisk Technologies LLCInventors: Yanjie Wang, Ohwon Kwon, Kou Tei, Tai-Yuan Tseng, Yasue Yamamoto, Yonggang Wu, Guirong Liang
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Publication number: 20230253053Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings. The memory cells are configured to retain a threshold voltage. The rows include full circle rows and semi-circle rows in which the memory holes are partially cut by a slit half etch. The memory holes of the semi-circle rows are coupled semi-circle bit lines and the memory holes of the full circle rows are coupled to full circle bit lines. A control means is configured to erase the memory cells in an erase operation. During the erase operation, the control means creates a capacitive coupling between each of the semi-circle bit lines and at least one neighboring one of the full circle bit lines to increase a semi-circle erase voltage applied to each of the semi-circle bit lines.Type: ApplicationFiled: February 8, 2022Publication date: August 10, 2023Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Kou Tei, Ohwon Kwon
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Publication number: 20230101019Abstract: Technology for mitigating interference to select transistors in 3D memory is disclosed. In one aspect, a control circuit pre-charges a first set of bit lines to a first voltage and pre-charges a second set of bit lines to a second voltage greater than the first voltage. The control circuit may increase the voltage on the first set of bit lines to the second voltage while the second set of bit lines are floating to couple up the voltages on the second set of bit lines to a voltage greater than the second voltage. The higher voltage on the second set of bit lines compensates for interference that some of the select transistors may experience from an adjacent select line. For example, the higher voltage can prevent a leakage current in the select transistors from occurring. Preventing the leakage current can improve boosting of NAND channel voltages, thereby preventing program disturb.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Kou Tei, Ohwon Kwon
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Patent number: 11521675Abstract: A data storage system includes a storage medium coupled to a storage controller via an electrical interface connected to a plurality of input/output (IO) pads of the storage medium. The storage medium receives a read or write instruction from the storage controller via the IO pads, associates the read or write instruction with memory cells of a first block of a first plane of a plurality of planes of the storage medium, and adjusts a word line voltage level or a source line voltage level for the first block of the first plane based on (i) a position of the first plane with respect to the IO pads of the storage medium and (ii) a position of the first block within the first plane.Type: GrantFiled: June 16, 2021Date of Patent: December 6, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Kou Tei, Anirudh Amarnath, Ohwon Kwon
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Patent number: 11222694Abstract: A storage device is disclosed herein. The storage device, comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines; and a reference current generator circuit configured to receive an input voltage from a voltage supply and generate therefrom a plurality of outputs, each output of the plurality of outputs used to generate one or more bias voltages/currents for one or more control signals. The control circuitry is configured to: receive a refresh read operation command; and adapt operation of the reference current generator circuit based on receiving the refresh read operation command. This proposal is also applicable for other test modes, such as SA stress, soft and preprogram, and SA test modes.Type: GrantFiled: August 5, 2020Date of Patent: January 11, 2022Assignee: SanDisk Technologies LLCInventors: Sirisha Bhamidipati, Arka Ganguly, Ohwon Kwon, Chia-Kai Chou, Kou Tei
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Patent number: 11139022Abstract: An example of an apparatus includes a plurality of memory cells arranged in a plurality of NAND strings that are connected to a source line and a control circuit connected to the source line. The control circuit is configured to provide a first current to the source line to pre-charge the source line to a target voltage for sensing data states of the plurality of memory cells and provide a second current to the source line to return the source line to the target voltage in a recovery period between sensing data states. The control circuit is configured to provide the second current at any one of a plurality of current levels.Type: GrantFiled: June 22, 2020Date of Patent: October 5, 2021Assignee: SanDisk Technologies LLCInventors: Kou Tei, Ohwon Kwon, Jongyeon Kim, Chia-Kai Chou, Yuedan Li
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Patent number: 10984877Abstract: An apparatus and method for a multi-state verify of a memory array are provided. A sense circuit of a memory device is connected to a bit line of the memory array. The sense circuit includes a first voltage clamp, a second voltage clamp, and a program data latch disposed on the bit line. The first and second voltage clamps are biased to first and second voltages, respectively, where the first voltage is lower than the second voltage. When a high bias is applied to the program data latch, the program data latch is in an OFF state, and the first voltage clamp limits the bias on the bit line to the first voltage. When a low bias is applied to the program data latch, the program data latch is in an ON state, and the second voltage clamp limits the bias on the bit line to the second voltage.Type: GrantFiled: December 17, 2019Date of Patent: April 20, 2021Assignee: SanDiskTechnologies LLCInventors: Jongyeon Kim, Hiroki Yabe, Kou Tei, Chia-Kai Chou, Ohwon Kwon
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Publication number: 20210104271Abstract: A memory device is provided including physical block circuitry including a first lateral network arrangement and a second lateral network arrangement. Each of the first and second lateral network arrangements includes a single generator configured to output both a sense amplifier voltage VHSA and a data latch voltage VDDSA, in each of a first mode and a second mode. In the first mode, during which read and program verify and other operations may occur, the generator receives VHSA as a feedback signal and in the second mode, during which programming, POR, and EVFY operations may occur, the generator receives VDDSA as a feedback signal.Type: ApplicationFiled: October 4, 2019Publication date: April 8, 2021Applicant: SanDisk Technologies LLCInventors: Ohwon Kwon, Kou Tei, VSNK Chaitanya G.
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Patent number: 10971209Abstract: A memory device is provided including physical block circuitry including a first lateral network arrangement and a second lateral network arrangement. Each of the first and second lateral network arrangements includes a single generator configured to output both a sense amplifier voltage VHSA and a data latch voltage VDDSA, in each of a first mode and a second mode. In the first mode, during which read and program verify and other operations may occur, the generator receives VHSA as a feedback signal and in the second mode, during which programming, POR, and EVFY operations may occur, the generator receives VDDSA as a feedback signal.Type: GrantFiled: October 4, 2019Date of Patent: April 6, 2021Assignee: SanDisk Technologies LLCInventors: Ohwon Kwon, Kou Tei, VSNK Chaitanya G
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Patent number: 9318204Abstract: A non-volatile memory and method have programming circuitry that outputs a series of programming pulses of increasing voltage level to program in parallel a group of memory cells associated with a selected word line. Individual timing of the programming pulses such as rise and fall times of the pulse is optimally and dynamically adjusted according to the relative numbers of program-enabled and program-inhibited memory cells in the group associated with that pulse.Type: GrantFiled: October 7, 2014Date of Patent: April 19, 2016Assignee: SanDisk Technologies, Inc.Inventors: Han Chen, Man Lung Mui, Kou Tei
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Publication number: 20160099059Abstract: A non-volatile memory and method have programming circuitry that outputs a series of programming pulses of increasing voltage level to program in parallel a group of memory cells associated with a selected word line. Individual timing of the programming pulses such as rise and fall times of the pulse is optimally and dynamically adjusted according to the relative numbers of program-enabled and program-inhibited memory cells in the group associated with that pulse.Type: ApplicationFiled: October 7, 2014Publication date: April 7, 2016Inventors: Han Chen, Man Lung Mui, Kou Tei
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Patent number: 5589975Abstract: An optical amplification system capable of operating without being affected by the waveform of the incoming optical signal is provided for amplifying the optical signal in its optical waveguide by the effect of stimulated emission of a fluorescent substance induced by pumped light. According to a first aspect of the invention, an optical amplification system turns on its pumping source 8 when there is an optical signal s1 in the optical waveguide 5 whereas the pumping source 8 is kept off as long as no optical signal s1 is found in the optical waveguide 5 so that, when the pumping source 8 is turned on, pumped light from the pumping source 8 is fed to the optical waveguide 5 with a delay of time relative to the incoming optical signal s1.Type: GrantFiled: November 4, 1994Date of Patent: December 31, 1996Assignee: The Furukawa Electric Co., Ltd.Inventors: Kazunori Nakamura, I. Kou Tei