Abstract: A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench.

Abstract: A power MOSFET is disclosed. In the power MOSFET, an epitaxial layer doped with dopants of a first conduction type is formed on a substrate. A first trench extends downward from a first region of the top surface of the epitaxial layer, and a second trench extends downward from the bottom of the first trench. The width of the second trench is smaller than that of the first trench. The first well is located adjacent to the bottom of the first trench and the bottom of the second trench, and is doped with dopants of a second conduction type. The second well extends downward from a second region of the top surface and is doped with dopants of the second conduction type. The first well and the second well are separated. A source region doped with dopants of the first conduction type is formed in the second well.

Abstract: A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, at least a doped region, an electrical contact layer and a metal oxide semiconductor cell. The semiconductor substrate includes opposing first and second surfaces and at least a trench extending from the second surface into interior portion thereof. The doped region is located in the semiconductor substrate under the bottom of the trench. The dopant concentration of the doped region is higher than that of the semiconductor substrate. The electrical contact layer is located on the second surface of the semiconductor substrate and connects to the doped region. The metal oxide semiconductor cell is located on the semiconductor substrate adjacent the first surface thereof.

Abstract: A power MOSFET including a substrate of first conductivity type, an epitaxial layer of first conductivity type on the substrate, a body layer of second conductivity type in the epitaxial layer, a first insulating layer, a second insulating layer, a first conductive layer and two source regions of first conductivity type is provided. The body layer has a first trench therein. The epitaxial layer has a second trench therein. The second trench is below the first trench, and the width of the second trench is much smaller than that of the first trench. The first insulating layer is at least in the second trench. The first conductive layer is in the first trench. The second insulating layer is at least between the sidewall of the first trench and the first conductive layer. The source regions are disposed in the body layer beside the first trench respectively.

Abstract: A power MOSFET is disclosed. In the power MOSFET, an epitaxial layer doped with dopants of a first conduction type is formed on a substrate. A first trench extends downward from a first region of the top surface of the epitaxial layer, and a second trench extends downward from the bottom of the first trench. The width of the second trench is smaller than that of the first trench. The first well is located adjacent to the bottom of the first trench and the bottom of the second trench, and is doped with dopants of a second conduction type. The second well extends downward from a second region of the top surface and is doped with dopants of the second conduction type. The first well and the second well are separated. A source region doped with dopants of the first conduction type is formed in the second well.

Abstract: A method of mounting flip-chip for lowering the on-resistance of power transistor in the protection circuit of rechargeable battery, which comprises a power field effect transistor and a protection IC, has the following steps: first, serially connect drain metal contacts of two transistors to form a chip cell during fabrication of wafer; then, use welding torch to point weld the metal wire on contact of each chip cell, so that the source and gate contacts will form welding metal bumps respectively; cut the wafer to form bare chip cells of two serially connected gate electrodes; stain said chip cell with tin so that said welding metal bumps on contacts are attached with tin balls; apply plastic material to positioned points of printed circuit board; use flip-chip technology to make drain of a bare chip cell face upward, so that said tin balls are aligned with the positioned points of printed circuit board; finally, passing through an oven for heating and pressuring, so that said tin balls will fuse and said pl

Abstract: A wireless bonded semiconductor device comprises a semiconductor chip packaged on a metal lead frame, in which the semiconductor chip contains at least one contact electrically connected to a lead frame and a connecting-pin terminal leading out from its bottom face, and at least one contact and a plurality of individual connecting-pin terminals leading out from its top face, there is no metal bonding wire exists between the surface contact and individual connecting-pin terminals, instead a matrix of the connecting-pin terminal with pre-determined extension length that directly folded and bonded onto the surface contact of the semiconductor chip is employed.

Abstract: A method of mounting flip-chip for lowering the on-resistance of power transistor in the protection circuit of rechargeable battery, which comprises a power field effect transistor and a protection IC, has the following steps: first, serially connect drain metal contacts of two transistors to form a chip cell during fabrication of wafer; then, use welding torch to point weld the metal wire on contact of each chip cell, so that the source and gate contacts will form welding metal bumps respectively; cut the wafer to form bare chip cells of two serially connected gate electrodes; stain said chip cell with tin so that said welding metal bumps on contacts are attached with tin balls; apply plastic material to positioned points of printed circuit board; use flip-chip technology to make drain of a bare chip cell face upward, so that said tin balls are aligned with the positioned points of printed circuit board; finally, passing through an oven for heating and pressuring, so that said tin balls will fuse and said pl

Abstract: A wireless bonded semiconductor device comprises a semiconductor chip packaged on a metal lead frame, in which the semiconductor chip contains at least one contact electrically connected to a lead frame and a connecting-pin terminal leading out from its bottom face, and at least one contact and a plurality of individual connecting-pin terminals leading out from its top face, there is no metal bonding wire exists between the surface contact and individual connecting-pin terminals, instead a matrix of the connecting-pin terminal with pre-determined extension length that directly folded and bonded onto the surface contact of the semiconductor chip is employed.

Abstract: A wireless bonded semiconductor device comprises a semiconductor chip packaged on a metal lead frame, in which the semiconductor chip contains at least one contact electrically connected to a lead frame and a connecting-pin terminal leading out from its bottom face, and at least one contact and a plurality of individual connecting-pin terminals leading out from its top face, there is no metal bonding wire exists between the surface contact and individual connecting-pin terminals, instead a matrix of the connecting-pin terminal with pre-determined extension length that directly folded and bonded onto the surface contact of the semiconductor chip is employed.

Abstract: A method of mounting flip-chip for lowering the on-resistance of power transistor in the protection circuit of rechargeable battery, which comprises a power field effect transistor and a protection IC, has the following steps: first, serially connect drain metal contacts of two transistors to form a chip cell during fabrication of wafer; then, use welding torch to point weld the metal wire on contact of each chip cell, so that the source and gate contacts will form welding metal bumps respectively; cut the wafer to form bare chip cells of two serially connected gate electrodes; stain said chip cell with tin so that said welding metal bumps on contacts are attached with tin balls; apply plastic material to positioned points of printed circuit board; use flip-chip technology to make drain of a bare chip cell face upward, so that said tin balls are aligned with the positioned points of printed circuit board; finally, passing through an oven for heating and pressuring, so that said tin balls will fuse and said pl