Patents by Inventor Koudou Yamauchi
Koudou Yamauchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7317658Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.Type: GrantFiled: March 17, 2006Date of Patent: January 8, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshio Takazawa, Toshio Yamada, Shinichi Ozawa, Takeo Kanai, Minoru Katoh, Koudou Yamauchi, Toshihiro Araki
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Patent number: 7154804Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.Type: GrantFiled: March 17, 2006Date of Patent: December 26, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshio Takazawa, Toshio Yamada, Shinichi Ozawa, Takeo Kanai, Minoru Katoh, Koudou Yamauchi, Toshihiro Araki
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Publication number: 20060187734Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.Type: ApplicationFiled: March 17, 2006Publication date: August 24, 2006Inventors: Yoshio Takazawa, Toshio Yamada, Shinichi Ozawa, Takeo Kanai, Minoru Katoh, Koudou Yamauchi, Toshihiro Araki
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Publication number: 20060164906Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.Type: ApplicationFiled: March 17, 2006Publication date: July 27, 2006Inventors: Yoshio Takazawa, Toshio Yamada, Shinichi Ozawa, Takeo Kanai, Minoru Katoh, Koudou Yamauchi, Toshihiro Araki
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Patent number: 7046573Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.Type: GrantFiled: December 31, 2003Date of Patent: May 16, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems, Co.,, Ltd.Inventors: Yoshio Takazawa, Toshio Yamada, Shinichi Ozawa, Takeo Kanai, Minoru Katoh, Koudou Yamauchi, Toshihiro Araki
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Publication number: 20040151033Abstract: Power wastefully consumed in a memory in standby state is reduced without lowering the speed of operation of reading data out of the memory. A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.Type: ApplicationFiled: December 31, 2003Publication date: August 5, 2004Applicants: Renesas Technology Corp, Hitachi ULSI Systems Co., Ltd.Inventors: Yoshio Takazawa, Toshio Yamada, Shinichi Ozawa, Takeo Kanai, Minoru Katoh, Koudou Yamauchi, Toshihiro Araki
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Patent number: 4879681Abstract: A semiconductor memory device includes an input circuit and an output circuit. To prevent the erroneous operation of the input circuit by the noise which develops at the time of the change of the output signal of the output circuit, the threshold voltage of the input circuit is changed, or an internal signal generated by the internal circuit is fixed to a predetermined level. In an output circuit having a tri-state output function, the threshold voltage of the input circuit is changed when the output is brought into the high impedance state, or the internal signal generated by the input circuit is fixed to a predetermined state. Using these arrangements it is possible to prevent the erroneous operation of the input circuit by the noise occurring when the output is brought into the high impedance state.Type: GrantFiled: January 5, 1989Date of Patent: November 7, 1989Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Hideo Miwa, Kazuhiro Tsuruoka, Koudou Yamauchi, Hitoshi Endoh, Masanori Odaka