Abstract: There are provided a memory space allocation method and a memory space allocation device that aim at higher-speed accesses when a memory is shared by a plurality of circuits. In this memory, one data is accessed by issuing addresses a plurality of times. Memory allocation is performed so that high-order addresses of memory spaces of an external memory 505 may be maximally shared by a plurality of circuits 501. When the high-order addresses are common, a memory control circuit does not transfer the high-order addresses, thereby reducing the number of transfers of the high-order addresses. Therefore, the higher-speed access is achieved.

Abstract: The transmission side device 10 is provided with a memory MT for holding a plurality of transmission signals transmitted last time and the reception side device 20 is provided with a memory MR for holding a plurality of reception signals received last time, thereby checking existence/non-existence of a change of a transmission signal to be transmitted this time by a comparator C. The transmission unit 103 transmits the changed part signal SL for discriminating a changed signal and the change end signal SE. The reception side device 20 equivalently receives a transmission signal as of this time by detecting and changing a changed signal among signals held in the memory MR based on the changed part signal SL. The clock generation unit 30 changes the circuit operation clock CLKC to advance the transmission circuit 101 and the reception circuit 201 by one cycle by receiving the change end signal SE.

Abstract: A circuit to be verified is divided into a plurality of circuit parts. A plurality of programmable devices are provided for implementing functional operation of the divided circuit parts through a simulation. Wiring used in the circuit to be verified for supplying a signal SX to be given at the same time to the plurality of programmable devices is provided so that a maximum skew of time at which the signal SX arrives at the plurality of programmable devices is less than a minimum time required for data transfer between the programmable devices. An input terminal PX for inputting the signal SX from a signal generation device (400) is implemented in each of the programmable devices. The signal SX can be inputted directly from the signal generation device, and a skew can be inhibited from being produced.

Abstract: There are provided a memory space allocation method and a memory space allocation device that aim at higher-speed accesses when a memory is shared by a plurality of circuits. In this memory, one data is accessed by issuing addresses a plurality of times. Memory allocation is performed so that high-order addresses of memory spaces of an external memory 505 may be maximally shared by a plurality of circuits 501. When the high-order addresses are common, a memory control circuit does not transfer the high-order addresses, thereby reducing the number of transfers of the high-order addresses. Therefore, the higher-speed access is achieved.

Abstract: The transmission side device 10 is provided with a memory MT for holding a plurality of transmission signals transmitted last time and the reception side device 20 is provided with a memory MR for holding a plurality of reception signals received last time, thereby checking existence/non-existence of a change of a transmission signal to be transmitted this time by a comparator C. The transmission unit 103 transmits the changed part signal SL for discriminating a changed signal and the change end signal SE. The reception side device 20 equivalently receives a transmission signal as of this time by detecting and changing a changed signal among signals held in the memory MR based on the changed part signal SL. The clock generation unit 30 changes the circuit operation clock CLKC to advance the transmission circuit 101 and the reception circuit 201 by one cycle by receiving the change end signal SE.