Abstract: A computer system has a master device having a first register for storing a first process ID associated with a software process number. The master device transmits the first process ID onto a system bus when it generates a transaction. The computer system has a slave device holding a second process ID for permitting access. The slave device accepts the transaction when the first process ID and the second process ID meet a predetermined condition.

Abstract: A computer system has a master device having a first register for storing a first process ID associated with a software process number. The master device transmits the first process ID onto a system bus when it generates a transaction. The computer system has a slave device holding a second process ID for permitting access. The slave device accepts the transaction when the first process ID and the second process ID meet a predetermined condition.

Abstract: A debugger includes: a break detecting circuit which, when the state of a microprocessor core corresponds to a previously set condition, generates a break request signal for requesting a transition of the microprocessor core to a debug state; a trigger detecting circuit which, when a predetermined signal of additional hardware corresponds to a previously set condition, generates a trigger request signal for requesting observation of the predetermined signal; and, an execution control circuit which, when the trigger request signal has been transmitted, outputs a trigger signal for observing the predetermined signal by means of a logic analyzer and outputs a break signal for causing the microprocessor core to transition to the debug state.

Abstract: An AES encryption processor is provided for reducing hardware with improved throughput. The processor is composed of a selector unit selecting an element of a state in response to row and column indices, a S-box for obtaining a substitution value with said selected element used as an index, a coefficient table providing first to fourth coefficients in response to said row index, first to fourth Galois field multiplexers respectively computing first to fourth products, which are obtained by multiplication of said substitution value with first to fourth coefficients, respectively, and an accumulator which accumulates the first to fourth products to develop first to fourth elements of a designated column of a resultant state.

Abstract: A debugger includes: a break detecting circuit which, when the state of a microprocessor core corresponds to a previously set condition, generates a break request signal for requesting a transition of the microprocessor core to a debug state; a trigger detecting circuit which, when a predetermined signal of additional hardware corresponds to a previously set condition, generates a trigger request signal for requesting observation of the predetermined signal; and, an execution control circuit which, when the trigger request signal has been transmitted, outputs a trigger signal for observing the predetermined signal by means of a logic analyzer and outputs a break signal for causing the microprocessor core to transition to the debug state.

Abstract: An AES encryption processor is provided for reducing hardware with improved throughput. The processor is composed of a selector unit selecting an element of a state in response to row and column indices, a S-box for obtaining a substitution value with said selected element used as an index, a coefficient table providing first to fourth coefficients in response to said row index, first to fourth Galois field multiplexers respectively computing first to fourth products, which are obtained by multiplication of said substitution value with first to fourth coefficients, respectively, and an accumulator which accumulates the first to fourth products to develop first to fourth elements of a designated column of a resultant state.

Abstract: A motion compensation adder for increasing a motion compensation processing speed is provided in a microprocessor having a multiply-accumulate instruction. A pixel value of a predicted picture which is expressed by an unsigned value is loaded into a register, and the most significant bit is inverted to format-convert the pixel value to a signed value with -128-offset. When hexadecimal constant 0.times.01000000 as a multiplicand, a signed error value as a multiplier and the format-converted pixel value of the predicted picture stored in the most significant byte of the register as an addition value are supplied to a multiply-accumulate instruction having a clipping function, the multiply-accumulate instruction performs the addition of the pixel value of the predicted picture and the error value and the clipping processing needed for the motion compensation adding processing by only one instruction.

Abstract: The invention provides a multiply-adder unit which has a reduced number of inputs to an adder tree to allow reduction of the amount of hardware and high speed operation. A bit width extender performs, upon unsigned operation, zero extension of one bit but performs, upon signed operation, sign extension of one bit for a multiplicand. A zero extender performs zero extension of 2 bits for a multiplier. A Booth's decoder cuts out an output of the zero extender in units of 3 bits successively shifting its cut-out start position by 2 bits toward the lower bits beginning with the uppermost bit and generates first to (k-1)th partial products and a kth partial product based on the cut out values and the output of the bit width extender. A selector selects, upon unsigned operation, the kth partial product but selects, upon signed operation, the output of the sign extender (addend after sign extension). A k-input adder tree adds the first to (k-1)th products and the output of the selector.

Abstract: The invention provides an addition overflow detection circuit which can detect an addition overflow at a high rate even where the output bit number is remarkably smaller than the input bit number and which is realized with a comparatively small amount of hardware. An unsigned augend and an unsigned addend of the n bit length are individually divided into lower m bits and upper n-m bits. The lower bits are inputted to an adder, and a carry from the (m-1)th bit to the mth bit is detected from the output of the adder. The upper bits are inputted to both of two fast adder-comparators, by which it is detected that all bits of the sum of them are equal to 1 or 0, respectively. In response to presence or absence of the carry, one of detection outputs of the fast adder-comparators is selected and logically inverted to obtain an overflow detection result.

Abstract: From a data memory, there is obtained data at an address indicated by the sum of the values respectively of a base register, an index register, and an offset. The data is stored in a data register. A wrap-around process is executed after an arithmetic operation is conducted by an arithmetic unit n times, n being specified by the value loaded in a block-length register. When the value of the index register is equal to or more than that of the element number register, the value of the element number register is subtracted from that of the index register. Since there exists a chance in which arithmetic operation is achieved beyond a circular buffer area allocated in the data memory, a copy of the first portion of the circular buffer is provided after the circular buffer area. Only one wrap-around process is executed each time a plurality of arithmetic operations are conducted, thereby implementing a high-speed circular buffer.