Abstract: A method of embedding an additional layer of error correction into an error correcting code, where information is encoded into code words that are arranged in columns of a code block. The method includes reducing the length of each row of the code block by adding row symbols together according to a predetermined adding rule resulting in a reduced code block; encoding the shortened rows of the reduced code block using a horizontal error correcting code to obtain horizontal parities; and embedding the horizontal parities as additional layer in the error correcting code.

Abstract: To appropriately express an erasure position of a code by a small-scale, simple-structured circuit, a soft-output decoding circuit (90) in each element decoder includes a received value and a priori probability information selection circuit (154) to select an input to-be-decoded received value TSR and extrinsic information or interleaved data TEXT, whichever is necessary for soft-output decoding. Based on inner erasure position information IERS supplied from an inner erasure information generating circuit (152), the received value and a priori probability information selection circuit (154) replaces a position where no coded output exists due to puncture or the like with a symbol whose likelihood is “0”. That is, the received value and a priori probability information selection circuit (154) outputs information which assures a probability in which a bit corresponding to a position where there is no coded output is “0” or “1” to be “½”.

Abstract: A decoder that receives, as input, probability information AMP/CR×yt. This probability information is obtained by dividing a channel value obtained by multiplication of received value yt and a predetermined coefficient AMP by the first additive coefficient CR for regulating the amplitude of the received value yt and the probability information 1/CA×APPt obtained by multiplying the a priori probability information APPt by the reciprocal of the second additive coefficient CA for regulating the amplitude of the a priori probability information APPt to a soft-output decoding circuit. The soft-output decoding circuit, which may be a large scale intergrated circuit, generates log soft-output CI×I?t and/or external information 1/CA×EXt using additive coefficients for regulating the amplitude of arithmetic operations in the inside of the soft-output decoding circuit.

Abstract: Error correction coding and decoding according to a serial concatenated modulation system are carried out under high code rate. A coding apparatus 1 comprises three convolutional coders 10, 30 and 50 for carrying out convolutional operation; two interleavers 20 and 40 for rearranging order of data input; and a multi-value mapping circuit 60 for carrying out mapping of a single point on the basis of a predetermined modulation system. The coding apparatus 1 carries out convolutional operation whose code rate is “?” as coding of extrinsic codes by a convolutional coder 10, and carries out convolutional operation whose code rate is “1” as coding of inner codes by a convolutional coder 50, and a multi-value modulation mapping circuit 60 applies mapping to a transmission symbol of a 8 PSK modulation system to output it as a single code transmission symbol.

Abstract: The present invention relates to a method of embedding an additional layer of error correction into an error correcting code, wherein information is encoded into code words of said code over a first Galois field and wherein a number of code words rare arranged in the columns of a code block comprising a user data sub-block and a parity data sub-block In order to provide an additional layer of error correction that can be easily implemented without losing compatibility improving the error correction capabilities, a method is proposed comprising the steps of:—encoding the rows of at least said user data sub-block separately or in groups using a horizontal error correcting code over a second Galois field larger than said first Galois field to obtain horizontal parities,—embedding said horizontal parities as additional layer in said error correcting code.

Abstract: The present invention relates to a method of embedding an additional layer of error correction into an error correcting code such as a product code in a DVD or a picket code in a DVR, wherein information is encoded into code words of said code and wherein a number of code words are arranged in the columns of code block. In order to provide an additional layer of error correction that can be easily implemented without losing compatibility improving the error correction capabilities a method is proposed comprising the steps of: reducing the length of each row of said code block by adding row symbols together according to a predetermined adding rule resulting in a reduced code block, encoding the shortened rows of said reduced code block using a horizontal error correcting code to obtain horizontal parities, embedding said horizontal parities as additional layer in said error correcting code.

Abstract: To carry out error correction coding and decoding according to a serially concatenated coded modulation system with a small circuit scale and high performance. A coding apparatus 1 is designed so that an interleaver 20 interleaves order of bits so that all weights are coded by a convolutional coder 30 with respect to data comprising a series of 3 bits supplied from a convolutional coder 10; the convolutional coder 30 makes as small as possible the total value of the hamming distance of input bit between passes to be the minimum Euclidean distance with respect to data of 3 bits supplied from the interleaver 20; and a multi-value modulation mapping circuit 40 causes the hamming distance of input bits in the convolutional coder 30 as the distance between signal point on the I/Q plane is smaller to subject data of 3 bits supplied from the convolutional coder 30 to mapping.

Abstract: To decode a code by a small-scale, simple circuit construction, an element decoder (50) includes a to-be-decoded received data selection circuit (70) to select a to-be-decoded received data TSR. The element decoder (50) selects the to-be-decoded received value TSR by the to-be-decoded received value selection circuit (70), based on received value selection information CSR supplied from a control circuit (60), and supplies it to a soft-output decoding circuit (90).

Abstract: To implement plural types of interleaving for decoding each of various codes in an adaptively suitable manner for the code by a simple circuit construction, an interleaver (100) in an element decoder includes a plurality of data storage circuits (407), and in addition, a control circuit (400) which generates address data for use to write data to the storage circuits (407) and address data for use to read date from the storage circuits (400), an address data selection circuit (405) which selects address data to be distributed to the plurality of storage circuits (407) according to a mode indicating the configuration of a code including the type of an interleaving to be done, an input data selection circuit (406) which selects data to be distributed to the plurality of storage circuits (407) according to the mode, and an output data selection circuit (408) which selects data to be outputted according to the mode. Of the plural storage circuits (407), a one to be used is selected.

Abstract: A decoder (3′) inputs the probability information AMP/CR×yt obtained by dividing the channel value obtained by multiplication of received value yt and a predetermined coefficient AMP by the first additive coefficient CR for regulating the amplitude of the received value yt and the probability information 1/CA×APPt obtained by multiplying the a priori probability information APPt by the reciprocal of the second additive coefficient CA for regulating the amplitude of the a priori probability information APPt to a soft-output decoding circuit 23 formed on a single semiconductor substrate as a large scale integrated circuit. The soft-output decoding circuit (23) generates log soft-output CI×I&lgr;t and/or external information 1/CA×EXt, using the first additive coefficient CR, the second additive coefficient CA and the third additive coefficient CI for regulating the amplitude of arithmetic operations in the inside of the soft-output decoding circuit (23).

Abstract: To appropriately express an erasure position of a code by a small-scale, simple-structured circuit, a soft-output decoding circuit (90) in each element decoder includes a received value and a priori probability information selection circuit (154) to select an input to-be-decoded received value TSR and extrinsic information or interleaved data TEXT, whichever is necessary for soft-output decoding. Based on inner erasure position information IERS supplied from an inner erasure information generating circuit (152), the received value and a priori probability information selection circuit (154) replaces a position where no coded output exists due to puncture or the like with a symbol whose likelihood is “0”. That is, the received value and a priori probability information selection circuit (154) outputs information which assures a probability in which a bit corresponding to a position where there is no coded output is “0” or “1” to be “½”.

Abstract: A decoder has a reduced circuit dimension that does not adversely affect the decoding performance of the circuit. The decoder includes an addition/comparison/selection circuit added to give the log likelihood and adapted to compute a correction item expressed in a one-dimensional function relative to a variable and add a predetermined value to the correction term in order to provide a unified symbol for identifying the positiveness or negativeness of the log likelihood for the purpose of computing the log likelihood.

Abstract: Multiword information is based on multibit symbols disposed in relative contiguity with respect to a medium, and is encoded with a wordwise interleaving and wordwise error protection code for providing error locative clues across multiword groups. In particular, the clues originate in high protectivity clue words (BIS) that are interleaved among clue columns, and also in synchronizing columns constituted from synchronizing bit groups. The synchronizing columns are located where the clue columns are relatively scarcer disposed. The clues are directed to low protectivity target words (LDS) that are interleaved in a substantially uniform manner among target columns which form uniform-sized column groups between periodic arrangements of clue columns and synchronizing columns.

Abstract: The present invention provides a decoder with a reduced circuit dimension without adversely affecting the decoding performance of the circuit. The decoder comprises an addition/comparison/selection circuit 60 added to give the log likelihood and adapted to compute a correction term expressed in a one-dimensional function relative to a variable and add a predetermined value to the correction term in order to provide a unified symbol for identifying the positiveness or negativeness of the log likelihood for the purpose of computing the log likelihood.

Abstract: To carry out error correction coding and decoding according to a serially concatenated coded modulation system with a small circuit scale and high performance. A coding apparatus 1 is designed so that an interleaver 20 interleaves order of bits so that all weights are coded by a convolutional coder 30 with respect to data comprising a series of 3 bits supplied from a convolutional coder 10; the convolutional coder 30 makes as small as possible the total value of the hamming distance of input bit between passes to be the minimum Euclidean distance with respect to data of 3 bits supplied from the interleaver 20; and a multi-value modulation mapping circuit 40 causes the hamming distance of input bits in the convolutional coder 30 as the distance between signal point on the I/Q plane is smaller to subject data of 3 bits supplied from the convolutional coder 30 to mapping.

Abstract: Error correction coding and decoding according to a serial concatenated modulation system are carried out under high code rate. A coding apparatus 1 comprises three convolutional coders 10, 30 and 50 for carrying out convolutional operation; two interleavers 20 and 40 for rearranging order of data input; and a multi-value mapping circuit 60 for carrying out mapping of a single point on the basis of a predetermined modulation system. The coding apparatus 1 carries out convolutional operation whose code rate is “⅔” as coding of extrinsic codes by a convolutional coder 10, and carries out convolutional operation whose code rate is “1” as coding of inner codes by a convolutional coder 50, and a multi-value modulation mapping circuit 60 applies mapping to a transmission symbol of a 8 PSK modulation system to output it as a single code transmission symbol.