Patents by Inventor Kouichi Hirae

Kouichi Hirae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7414323
    Abstract: Input test pads of an adjacent pattern area are placed in a vacant area of a layout area of output test pads, optimizing the layout area of test pads for use in inspection of a semiconductor chip. Thus, it is possible to miniaturize a semiconductor package.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: August 19, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kouichi Hirae
  • Publication number: 20060181299
    Abstract: Input test pads of an adjacent pattern area are placed in a vacant area of a layout area of output test pads, optimizing the layout area of test pads for use in inspection of a semiconductor chip. Thus, it is possible to miniaturize a semiconductor package.
    Type: Application
    Filed: February 2, 2006
    Publication date: August 17, 2006
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kouichi Hirae