Patents by Inventor Kouichi Hirosawa

Kouichi Hirosawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040104463
    Abstract: A laminated flip-chip interconnect package comprising a substrate having a chip attach surface and a board attach surface that define contact pads for attachment to corresponding pads on the chip and board wherein the substrate board surface comprises at least one solid plane covering the chip attach surface region near at least one chip corner. In one embodiment, the solid plane comprises a dielectric material, optionally covered with a soldermask or coverlay material. In an alternate embodiment, the solid plane comprises a metal, optionally covered with a soldermask or coverlay material.
    Type: Application
    Filed: September 23, 2003
    Publication date: June 3, 2004
    Inventors: Robin E. Gorrell, Mark F. Sylvester, Donald R. Banks, Michael D. Holcomb, William V. Ballard, Kouichi Hirosawa, Sadanobu Satou, Teruhiko Kimura
  • Patent number: 5578341
    Abstract: A method of manufacturing a printed wiring board by a build-up technique improves the bonding force between a conductor circuit and a resin. After the surface of the first conductor pattern is roughened by oxidation, an insulating layer is formed to expose a viahole portion of the first conductor pattern. Then the resin insulating layer is roughened and the board is reduction processed before a plating operation is carried out.
    Type: Grant
    Filed: December 27, 1994
    Date of Patent: November 26, 1996
    Assignee: NEC Corporation
    Inventor: Kouichi Hirosawa
  • Patent number: 5263243
    Abstract: In a method for producing a multilayer printed wiring board, first and second copper foils for surface layer are disposed on both sides of an inner wiring substrate so that each of first and second prepreg sheets provided with through-holes is sandwiched between each of the copper foils for surface layer and each face of the substrate, the through-holes being formed therethrough at desired positions corresponding to positions where the connecting pads on each face of the substrate are formed, and the resulting structure is integrally bonded by applying heat and pressure thereto. During the heat- and pressure-processing step, the through-holes within the prepreg sheets are filled with a resin fused from the prepreg sheets. After selectively removing the copper foil for surface layer within an area which matches each of the connecting pads, the resin is selectively removed by the irradiation of laser beams to form via holes and allow the connecting pads to be exposed.
    Type: Grant
    Filed: January 28, 1993
    Date of Patent: November 23, 1993
    Assignee: NEC Corporation
    Inventors: Junichi Taneda, Keisuke Okada, Takumi Hiroto, Kouichi Hirosawa