Patents by Inventor Kouichi Ikeda

Kouichi Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9809901
    Abstract: A method for manufacturing a silicon single crystal according to a Czochralski method to manufacture an N-type silicon single crystal, including the steps of: seeding to bring a seed crystal into contact with a silicon melt in a crucible and thereafter, necking to pull the seed crystal to narrow a diameter thereof, wherein a dopant concentration in the silicon melt is predicted by a difference between a temperature at the seeding and a temperature at the necking, and resistivity of the single crystal to be pulled is controlled on the basis of the predicted dopant concentration in the silicon melt. A method for manufacturing a silicon single crystal can efficiently manufacture a silicon single crystal with a desired resistivity.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: November 7, 2017
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Satoshi Soeta, Shinji Nakano, Kouichi Ikeda
  • Publication number: 20160237589
    Abstract: A method for manufacturing a silicon single crystal according to a Czochralski method to manufacture an N-type silicon single crystal, including the steps of: seeding to bring a seed crystal into contact with a silicon melt in a crucible and thereafter, necking to pull the seed crystal to narrow a diameter thereof, wherein a dopant concentration in the silicon melt is predicted by a difference between a temperature at the seeding and a temperature at the necking, and resistivity of the single crystal to be pulled is controlled on the basis of the predicted dopant concentration in the silicon melt. A method for manufacturing a silicon single crystal can efficiently manufacture a silicon single crystal with a desired resistivity.
    Type: Application
    Filed: October 16, 2014
    Publication date: August 18, 2016
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Satoshi SOETA, Shinji NAKANO, Kouichi IKEDA
  • Patent number: 8917103
    Abstract: A testing method for testing a semiconductor device includes heating the semiconductor device until the temperature of the semiconductor device reaches a predetermined temperature; conducting other functional tests other than testing of the overheat protection function in a second step after the temperature of the semiconductor device has reached the predetermined temperature; allowing the semiconductor device to generate heat by itself such that the overheat protection function of the semiconductor device is activated, detecting a first diode forward voltage of a desired diode contained in the semiconductor device when the overheat protection function of the semiconductor device is activated and computing a first computational temperature of the semiconductor device based on the detected first diode forward voltage of the desired diode contained in the semiconductor device; and determining whether the computed first computational temperature of the semiconductor device resides in the overheat protection func
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: December 23, 2014
    Assignee: Ricoh Company, Ltd.
    Inventors: Koichi Morino, Kouichi Ikeda
  • Patent number: 8860445
    Abstract: A testing method for testing a semiconductor device includes heating the semiconductor device until the temperature of the semiconductor device reaches a predetermined temperature; conducting other functional tests other than testing of the overheat protection function in a second step after the temperature of the semiconductor device has reached the predetermined temperature; allowing the semiconductor device to generate heat by itself such that the overheat protection function of the semiconductor device is activated, detecting a first diode forward voltage of a desired diode contained in the semiconductor device when the overheat protection function of the semiconductor device is activated and computing a first computational temperature of the semiconductor device based on the detected first diode forward voltage of the desired diode contained in the semiconductor device; and determining whether the computed first computational temperature of the semiconductor device resides in the overheat protection func
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: October 14, 2014
    Assignee: Ricoh Company, Ltd.
    Inventors: Koichi Morino, Kouichi Ikeda
  • Publication number: 20120032696
    Abstract: A testing method for testing a semiconductor device includes heating the semiconductor device until the temperature of the semiconductor device reaches a predetermined temperature; conducting other functional tests other than testing of the overheat protection function in a second step after the temperature of the semiconductor device has reached the predetermined temperature; allowing the semiconductor device to generate heat by itself such that the overheat protection function of the semiconductor device is activated, detecting a first diode forward voltage of a desired diode contained in the semiconductor device when the overheat protection function of the semiconductor device is activated and computing a first computational temperature of the semiconductor device based on the detected first diode forward voltage of the desired diode contained in the semiconductor device; and determining whether the computed first computational temperature of the semiconductor device resides in the overheat protection func
    Type: Application
    Filed: August 5, 2011
    Publication date: February 9, 2012
    Applicant: RICOH COMPANY, LTD.
    Inventors: Koichi Morino, Kouichi Ikeda
  • Publication number: 20080309772
    Abstract: A digital still camera includes a lens system having a variable focal length. An image pickup unit is disposed on an optical axis of the lens system, for forming an image frame. Yaw and pitch rate sensors detect a camera shake to output shake information. A shake correction mechanism, associated with an anti-vibration lens, compensates for the camera shake by shifting perpendicularly to the optical axis according to the shake information. A memory stores an LUT of correlation information between the focal length and a shift amount of the shake correction mechanism to compensate for an image shake of the image frame created due to a change in the focal length. In case of lack of detected camera shake with the yaw and pitch rate sensors, the shake correction mechanism is controlled with a shift amount associated with the focal length according to the LUT.
    Type: Application
    Filed: May 20, 2008
    Publication date: December 18, 2008
    Applicant: FUJIFILM CORPORATION
    Inventor: Kouichi Ikeda
  • Patent number: 6986417
    Abstract: A transfer system includes transfer lines (L) each of which forms a closed loop and has transfer-in stations (S1 and S3) and transfer-out stations (S2 and S4) for assembling parts to a work, while circulating the work along the transfer line (L); and a work and part transfer passage (51) for transferring the work and the parts. Transfer-in stations (S1 and S3) and the transfer-out stations (S2 and S4) are disposed at each of the longitudinal ends of each of the transfer lines (L). Sub-transfer-passages (521 and 522) branching out rightward and leftward from the work and part transfer passage (51), are disposed along longitudinal sides of the transfer lines (L). With this layout, a plurality of the transfer lines (L) can be disposed in a required minimum space, while securing a smooth supply and discharge of the works and parts with respect to the plurality of the transfer lines L.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: January 17, 2006
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Yoshihiro Nishizawa, Masami Mitsuhashi, Keiichi Kubota, Kouichi Ikeda, Hideo Murakami
  • Patent number: 6969623
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device mountable with high density, which includes a simplified process but is capable of reducing a defect rate. A plurality of identical memory chips are formed on a semiconductor wafer, and a go/no-go test is conducted on all the memory chips. The semiconductor wafer is cut and divided into pieces that each consists of one, or two, or four good memory chips, and they are mounted on a substrate to form a memory module.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: November 29, 2005
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventors: Kouichi Ikeda, Takeshi Ikeda
  • Patent number: 6626282
    Abstract: A transfer line (L) is formed by a first conveyer (C1) and a second conveyer (C2) which are disposed in parallel to each other for transferring a pallet, a first traverser (T1) for transporting the pallet (P) from a terminal end of the first conveyer (C1) to a start end of the second conveyer (C2), and a second traverser (T2) for transporting the pallet (P) from a terminal end of the second conveyer (C2) to a start end of the first conveyer (C1). The first and second conveyers (C1 and C2) are operable to drive main drive rollers (22) provided at start ends of the conveyers by bringing the rollers into abutment against side surfaces of rearmost pallets (P) in the advancing direction, thereby urging and collectively driving a plurality of pallets (P) which are connected together forwardly of the rearmost pallets (P) in a state in contact with the rearmost pallets. This enables the length of the transfer line (L) to be changed as desired without modification of a drive device for the pallet (P).
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: September 30, 2003
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Yoshihiro Nishizawa, Masami Mitsuhashi, Keiichi Kubota, Kouichi Ikeda, Hideo Murakami
  • Patent number: 6479306
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device mountable with high density, which includes a simplified process but is capable of reducing a defect rate. A plurality of semiconductor chips of different kinds (processor chip and memory chip) are formed on a semiconductor wafer, and a go/no-go test is conducted on all the chips. The semiconductor wafer is cut and divided into pieces that each consist of a good processor chip and a good memory chip, and they are mounted on a substrate to form a semiconductor module.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: November 12, 2002
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventors: Kouichi Ikeda, Takeshi Ikeda
  • Patent number: 6433462
    Abstract: An ultrasonic motor includes a stator, which includes a piezoelectric element, and a rotor, which opposes the stator. The piezoelectric element vibrates the stator to rotate the rotor. The rotor has an annular thin section. An elastic ring is secured to the thin section. The mass of the elastic ring is selected from a predetermined range of masses. The motor speed at which a predetermined level of noise is produced by the motor is substantially constant for the range of the masses. This reliably damps undesirable vibration of the motor.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: August 13, 2002
    Assignee: ASMO Co., Ltd.
    Inventors: Takashi Fukui, Kouichi Ikeda
  • Patent number: 6291309
    Abstract: A semiconductor device which is mounted with a plurality of semiconductor chips. The fraction defective is low when the device is manufactured, and the efficiency of inspection is high. A method for manufacturing such a semiconductor device is also disclosed. A plurality of kinds of semiconductor chips 1 are COB-mounted on a substrate 2 and the surface of the substrate 2 mounted with the chips 1 is encapsulated with a resin 3. Then all the chips 1 mounted on the substrate 2 are inspected at once. Semiconductor devices 10 are produced by cutting the substrate 2 into pairs of adjacently arranged two different kinds of semiconductor chips 1 together which are judged to be nondefective chips.
    Type: Grant
    Filed: May 16, 2000
    Date of Patent: September 18, 2001
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventors: Kouichi Ikeda, Takeshi Ikeda
  • Patent number: 6281026
    Abstract: A semiconductor device which is mounted with a plurality of semiconductor chips. The fraction defective is low when the device is manufactured, and the efficiency of inspection is high. A method for manufacturing such a semiconductor device is also disclosed. A plurality of identical bare chips 1 for memory are COB-mounted on a substrate 2, and the surface of the substrate 2 mounted with the chips 1 is encapsulated with a resin 3. Then all the chips 1 mounted on the substrate 2 are inspected at once. Four-chip, two-chip, and one-chip memory modules 10 are produced by cutting the substrate 2 and combining bare chips 1 which are judged to be nondefective chips.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: August 28, 2001
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventors: Kouichi Ikeda, Takeshi Ikeda
  • Publication number: 20010013740
    Abstract: An ultrasonic motor includes a stator, which includes a piezoelectric element, and a rotor, which opposes the stator. The piezoelectric element vibrates the stator to rotate the rotor. The rotor has an annular thin section. An elastic ring is secured to the thin section. The mass of the elastic ring is selected from a predetermined range of masses. The motor speed at which a predetermined level of noise is produced by the motor is substantially constant for the range of the masses. This reliably damps undesirable vibration of the motor.
    Type: Application
    Filed: February 2, 2001
    Publication date: August 16, 2001
    Applicant: ASMO CO., LTD.
    Inventors: Takashi Fukui, Kouichi Ikeda
  • Patent number: 6208546
    Abstract: An object of the present invention is to provide a memory module capable of being mounted easily on various memory boards or mother boards, having a large memory capacity, and requiring a small mounting area. The memory module 10 includes four memory bare chips 1 scribed from a semiconductor wafer and mounted on a module board 2 by the COB technology. The module board 2 is formed with a row of pads 4 near the center portion in the longitudinal direction of the module board 2. Two memory bare chips 1 are disposed on the module board 2 at opposite sides of the pads 4. Each memory bare chip 1 is formed with pads 3 along the center line and the pads 3 are connected to the pads 4 on the module board 2 by the use of bonding wires 5. The bonding wires 5 and the memory bare chips 1 are covered with a plastic resin 6. Also, the module board 2 is formed with external connection terminals 8 on the outer side edges for connection to a memory board or a mother board by the LCC technology.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: March 27, 2001
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventor: Kouichi Ikeda
  • Patent number: 4921426
    Abstract: The invention relates to a device for supplying power to a car-mounted apparatus by electrically connecting a connector on the car-body and a connector on the car-mounted apparatus, where either of these connectors is installed so that it can freely move and integrally vibrate with the other connector when in a mated condition.
    Type: Grant
    Filed: April 20, 1988
    Date of Patent: May 1, 1990
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Nobuhiko Kawasaki, Kouichi Ikeda, Shinichi Kimura
  • Patent number: 4767337
    Abstract: A device and system for connecting a car-mounted apparatus comprising a fixing plate installed to part of a car body for supporting the car-mounted apparatus, a female part formed in either the car-mounted apparatus or the fixing plate, and a male part extending from either the car-mounted apparatus or the fixing plate that can be freely engaged with and disengaged from the female part. The invention also relates to a device for supplying power to a car-mounted apparatus by electrically connecting a connector on the car-body and a connector on the car-mounted apparatus, where either of these connectors is installed so that it can freely move and integrally vibrate with the other connector when in an engaged condition.
    Type: Grant
    Filed: June 18, 1986
    Date of Patent: August 30, 1988
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Nobuhiko Kawasaki, Kouichi Ikeda, Shinichi Kimura