Patents by Inventor Kouichi Imura

Kouichi Imura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8045150
    Abstract: A semiconductor wafer inspection method includes: an imaging step in which a first image being an image of the chamfered surface seen from the main surface side and a second image being an image of the chamfered surface seen from the back surface side are taken; a calculation step in which a first width is obtained based on the first image, the first width being a width of the chamfered surface seen from the main surface side, a second width is obtained based on the second image, the second width being a width of the chamfered surface seen from the back surface side, and a ratio of the first width to the second width thus obtained is calculated; and a shape determination step in which a form of the chamfered surface is determined to be abnormal in a case where the ratio is out of a predetermined range.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: October 25, 2011
    Assignee: Sumco Techxiv Corporation
    Inventors: Kantarou Torii, Kouichi Imura
  • Publication number: 20100060891
    Abstract: A semiconductor wafer inspection method includes: an imaging step in which a first image being an image of the chamfered surface seen from the main surface side and a second image being an image of the chamfered surface seen from the back surface side are taken; a calculation step in which a first width is obtained based on the first image, the first width being a width of the chamfered surface seen from the main surface side, a second width is obtained based on the second image, the second width being a width of the chamfered surface seen from the back surface side, and a ratio of the first width to the second width thus obtained is calculated; and a shape determination step in which a form of the chamfered surface is determined to be abnormal in a case where the ratio is out of a predetermined range.
    Type: Application
    Filed: September 8, 2009
    Publication date: March 11, 2010
    Applicant: SUMCO TECHXIV CORPORATION
    Inventors: Kantarou TORII, Kouichi IMURA
  • Patent number: 6234873
    Abstract: A method for manufacturing semiconductor wafers is provided. According to this invention, wafers are obtained by slicing a single-crystal semiconductor ingot. The sliced wafers are beveled at their peripheral rims. The beveled wafers are flattened by a lapping process. The front and the rear surfaces of the flattened wafers are spin-etched with an acid etchant liquid. The glossiness of the rear surfaces of the spin-etched wafers is controlled to a value of 130-300 %. The front surfaces of the wafers whose rear surfaces have been spin-etched are polished, thereby obtaining mirror-polished surfaces. The front surfaces may also be spin-etched prior to polishing.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: May 22, 2001
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hiroaki Yamamoto, Akihiro Ishii, Kouichi Imura
  • Patent number: 5849636
    Abstract: A method processes a semiconductor wafer by etching the wafer, which has been smoothed by rough lapping, with alkaline solution. A rod is sliced into a plurality of wafers. The peripheral edges of the wafers are chamfered. The processed strain layers over the wafers due to chamfering are smoothed and planarized. The processed strain layers are then removed by etching with alkaline solution. The etched wafers are mirror polished. Lastly, the mirror-polished wafers are cleaned.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: December 15, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Takamitsu Harada, Kouichi Imura, Hisaya Fukunaga, Masahiko Maeda