Abstract: A clock signal is supplied from a clock oscillator to a gate circuit. In a period in which a reset signal is at the “H” level, the clock signal is supplied to an internal circuit. When the reset signal becomes at the “L” level, a control is performed by a gate control circuit so as to stop the supply of the clock signal. Consequently, even when a delay signal in the internal circuit becomes longer than one cycle of the clock signal, occurrence of an erroneous operation can be prevented.

Abstract: A current mirror circuit consisting of two P-channel MOS transistors in an operating current control section controls an operating current of a ring oscillator circuit in accordance with a current value of a constant current flowing in the current mirror circuit. A control voltage input section and a first current mirror resistance section in the operating current control section control the current value of the constant current generated by the current mirror circuit in accordance with a control voltage, and changes a range in which the constant current value is changed in response to a change of the control voltage, in accordance with a control signal.

Abstract: A clock generator includes a frequency divider for outputting a divided clock signal by dividing an input clock signal in accordance with a dividing ratio control signal; and a phase adjusting circuit for adjusting a phase of an internal clock signal with that of an external clock signal. The frequency divider further includes a dividing ratio control signal inhibiting circuit for disabling the dividing ratio control signal as long as a lock signal supplied from the phase adjusting circuit is active. The frequency divider generates a particular clock signal as long as the dividing ratio control signal is disabled, and changes the frequency of the divided clock signal by enabling the dividing ratio control signal in synchronism with the particular clock signal when the lock signal is made inactive.

Abstract: A current mirror circuit consisting of two P-channel MOS transistors in an operating current control section controls an operating current of a ring oscillator circuit in accordance with a current value of a constant current flowing in the current mirror circuit. A control voltage input section and a first current mirror resistance section in the operating current control section control the current value of the constant current generated by the current mirror circuit in accordance with a control voltage, and changes a range in which the constant current value is changed in response to a change of the control voltage, in accordance with a control signal.

Abstract: A clock signal is supplied from a clock oscillator to a gate circuit. In a period in which a reset signal is at the “H” level, the clock signal is supplied to an internal circuit. When the reset signal becomes at the “L” level, a control is performed by a gate control circuit so as to stop the supply of the clock signal. Consequently, even when a delay signal in the internal circuit becomes longer than one cycle of the clock signal, occurrence of an erroneous operation can be prevented.

Abstract: Clock generating circuitry includes a frequency dividing circuit for dividing the frequency of an input clock by each of a plurality of predetermined frequency dividing ratios which differ from each other to generate a plurality of frequency-divided clocks such that a frequency-divided clock generated with the smallest frequency dividing ratio, i.e., a frequency-divided clock having the highest frequency, is slightly delayed against all of the other generated frequency-divided clocks. When changing the frequency of an output clock, a multiplexer switches from a previously selected one of the plurality of generated frequency-divided clocks to a desired clock in responsive to a control signal. The desired frequency-divided clock is then furnished as the output clock.

Abstract: In a multiplying circuit for providing a pulsed output clock signal having a frequency that is a multiple of a pulsed input clock signal, a delay of a digital delay line is initialized by initializing a counter when an external reset signal is input and when the number of pulses of the output clock signal from the clock generator is smaller than a predetermined multiplier. The delay of the digital delay line is set to a minimum value immediately following the initialization and then increased gradually in order to output the desired output clock signal.

Abstract: Delay circuitry includes a phase-locked loop or PLL for comparing the phase of a reference clock applied thereto with that of another clock to be compared to generate a control signal having a value corresponding to the phase difference between the phases of the reference clock and other clock, for generating the other clock using at least a plurality of delay elements connected into a loop, a time delay provided by each of the plurality of delay elements being controlled by the control signal, and for changing the value of the control signal so that the other clock is made to be in phase with the reference clock.

Abstract: When a reset signal (PLL-RST) is input, an arithmetic unit (12) measures the cycle of an input clock (IN) with a pulse counter (9) and based on the measured cycle, calculates a count value such that a delay clock (DL-OUT) and an input clock (IN) may come into synchronization with each other, to set it to a counter (13). The counter (13) thereafter changes the count value step by step in accordance with an output signal from a phase comparator (18). After the count value of the counter (13) is set by the arithmetic unit (12), an arithmetic unit (30) calculates a count value such that an output clock (PLL-OUT) and the input clock (IN) may come into synchronization with each other, to set it to a counter (31). The counter (31) changes the count value step by step in accordance with an output signal from a phase comparator (35) only when the two phases compared by the phase comparator (18) coincide with each other. With this configuration, a transition period to achieve a stable output clock can be reduced.

Abstract: A oscillation circuit has a delay loop with a clock delay circuit for generating a delayed clock signal. The clock delay circuit has a selector and has multiple delay elements with delay times differing from each other. The clock delay circuit may produce a time lag which is less than the delay time of any single delay element, the time lag being based on the difference between the time delays of different delay elements. A phase comparator compares the phase of a signal associated the delay loop to that of a reference clock signal, generating a phase difference clock signal. A delay setting circuit can cause the selector to change the selection of one delayed clock signal according to the phase difference signal from the phase comparator in such a manner as to reduce the phase difference.

Abstract: In a multiplying circuit for providing a pulsed output clock signal have a frequency that is a multiple of a pulsed input clock signal, a delay of a digital delay line is initialized by initializing a counter when an external reset signal is input and when the number of pulses of the output clock signal from the clock generator is smaller than a predetermined multiplier. The delay of the digital delay line is set to a minimum value immediately following the initialization and then increased gradually in order to output the desired output clock signal.

Abstract: A clock generator including a frequency multiplier, a phase lock circuit and a frequency divider. The frequency multiplier generates a frequency multiplied clock by multiplying the frequency of an input clock. The phase lock circuit detects a phase difference between the input clock and a frequency divided clock, and generates, by delaying the frequency multiplied clock by an amount corresponding to the phase difference, a phase-locked clock with its phase locked with the input clock. The frequency divider detects in every fixed cycle a particular pulse of the phase-locked clock, and generates the frequency divided clock by dividing the phase-locked clock with reference to the particular pulse of the phase-locked clock. In particular, the frequency divider detects the particular pulse immediately previous to a falling edge of the input clock.

Abstract: A data processor, with high processing performance in many fields of application, having a selector 41 which enables a cache memory of direct map system to be selectively used as a built-in cache memory or a built-in RAM in order to realize a data processor which can perform high-speed processing by decreasing the number of abortions of the processing as much as possible when branch is predicted in the pipeline processing mechanism, and an FB register 61B which holds an address to be accessed so that cache memory or external storage (main storage 28) may be accessed when branch is not predicted in the pipeline processing mechanism and only a cache memory may be accessed but accessing to the main storage 28 may be prohibited when branch is predicted, wherein the main storage 28 can be accessed by the address held in the FB register 61B at the moment it becomes accessible.