Patents by Inventor Kouichi Kitano

Kouichi Kitano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070086491
    Abstract: A generating unit generates an apparatus reference frame phase that becomes a reference in a data multiplexing/demultiplexing apparatus, based on a reception frame phase of the data input to a predetermined reception buffer and a predetermined delay amount. A multiplexing/demultiplexing unit reads data from the reception buffer based on the apparatus reference frame phase generated by the generating unit, and multiplexes or demultiplexes the data.
    Type: Application
    Filed: January 27, 2006
    Publication date: April 19, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Kenichi Ishikawa, Kouichi Kitano, Tsuyoshi Matsumoto, Junichi Sawada
  • Patent number: 5577096
    Abstract: A transmission system provides a stand-by line switching facility. The transmission system includes a plurality of working line side processing equipments and a stand-by line side processing equipment to replace one of the working line side processing equipments if a fault occurs therein. The transmission system has a first unit and second unit disposed for each working line side processing equipment. The first unit issues, upon receipt of a line switching command, a single line switching control signal. The second units commonly receive the single line switching control signal and respective line switching is performed between the faulty working line and the stand-by line simultaneously.
    Type: Grant
    Filed: February 17, 1993
    Date of Patent: November 19, 1996
    Assignee: Fujitsu Limited
    Inventors: Kouichi Kitano, Atsuhiko Utsumi
  • Patent number: 4611303
    Abstract: A word-line discharging circuit in a static-type semiconductor memory device, including, for each word line, a first transistor for detecting the potential change of the word line, a time-constant circuit for delaying the output of the first transistor, and a second transistor for conducting a discharging current through the memory cells. The second transistor is switched in response to the output of the time-constant circuit, and includes, for all of the word lines, a common discharging current source. The word-line discharging circuit further includes means respectively provided between the word lines and the common discharging current source for respectively slowing the rate of change in the current flowing through the word lines, whereby double selection of the word lines is prevented.
    Type: Grant
    Filed: February 25, 1983
    Date of Patent: September 9, 1986
    Assignee: Fujitsu Limited
    Inventor: Kouichi Kitano
  • Patent number: 4601014
    Abstract: A semiconductor memory circuit including a charge absorbing circuit. The charge absorbing circuit absorbs at least a current induced by a voltage increase in the word line occurring soon after the word line is switched from a selection state to a nonselection state.
    Type: Grant
    Filed: March 17, 1983
    Date of Patent: July 15, 1986
    Assignee: Fujitsu Limited
    Inventors: Kouichi Kitano, Hideaki Isogai