Patents by Inventor Kouichi Konishi

Kouichi Konishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230378281
    Abstract: Increasing in a contact-resistance between a trench gate lead-out electrode and a gate lead-out contact member is suppressed. It is assumed that a natural oxidation film is formed in the polysilicon film when the trench gate lead-out electrode is formed. In case of the natural oxidation film is formed, a desired etching process is performed so that the natural oxidation film does not protrude beyond the upper surface of the trench gate lead-out electrode.
    Type: Application
    Filed: March 2, 2023
    Publication date: November 23, 2023
    Inventor: Kouichi KONISHI
  • Publication number: 20230335604
    Abstract: A source diffusion layer and a base diffusion layer are formed in regions of a semiconductor substrate located between a trench gate electrode and a trench emitter electrode that are spaced apart from each other. The trench emitter electrode, the base diffusion layer, and an insulating film have a recess that recede from a first main surface toward a second main surface. A shared contact member protrudes from the first main surface toward the second main surface in a manner contacting the recess. According to above structure of a semiconductor device, it is capable of efficiently discharging carriers to an emitter during turn-off.
    Type: Application
    Filed: January 10, 2023
    Publication date: October 19, 2023
    Inventor: Kouichi KONISHI
  • Patent number: 8395238
    Abstract: A semiconductor device including a substrate, and an insulating film formed over the substrate, wherein the insulating film has a first contact having a rectangular geometry in a plan view, and second to fifth contacts provided respectively adjacent to the individual edges of the rectangular first contact, formed therein.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: March 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Kouichi Konishi
  • Publication number: 20110127677
    Abstract: A semiconductor device including a substrate, and an insulating film formed over the substrate, wherein the insulating film has a first contact having a rectangular geometry in a plan view, and second to fifth contacts provided respectively adjacent to the individual edges of the rectangular first contact, formed therein.
    Type: Application
    Filed: February 7, 2011
    Publication date: June 2, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Kouichi Konishi
  • Patent number: 7906436
    Abstract: A method of manufacturing a semiconductor device which includes step of forming a lower resist film over an insulating interlayer; forming a first opening having a circular geometry in a plan view, and second to fifth openings arranged respectively on four sides of the first opening, in the lower resist film; and etching the film-to-be-etched while using the lower resist film as a mask, wherein in the step of etching the film-to-be-etched, a hardened layer is formed in a region of the lower resist film fallen between the first opening and each of the second to fifth openings, and the film-to-be-etched is etched while using the hardened layers as a mask, so as to form a contact hole having a rectangular geometry in a plan view in the film-to-be-etched at a position correspondent to the first opening of the lower resist film.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: March 15, 2011
    Assignee: RENESAS Electronics Corporation
    Inventor: Kouichi Konishi
  • Patent number: 7646096
    Abstract: A semiconductor device having good production stability and excellent in a contact property between an antireflection film on an Al contained metal film and a conductive plug. The device includes a substrate, an insulating interlayer, and a multi-layer structure. The insulating interlayer is formed in the upper portion of the substrate. The structure is provided on the insulating interlayer. A Ti film, a first TiN film, an AlCu film, a Ti film, a second TiN film, and an etching adjustment film are sequentially formed in the structure. The device includes an insulating interlayer and a conductive plug. The insulating interlayer is provided on the insulating interlayer and the structure. The conductive plug penetrates the insulating interlayer and the etching adjustment film, and an end surface of the conductive plug is located in the second TiN film. The conductive plug includes a Ti film, a TiN film, and a W film.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: January 12, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Masashige Moritoki, Kouichi Konishi
  • Publication number: 20090206475
    Abstract: A method of manufacturing a semiconductor device which includes step of forming a lower resist film over an insulating interlayer; forming a first opening having a circular geometry in a plan view, and second to fifth openings arranged respectively on four sides of the first opening, in the lower resist film; and etching the film-to-be-etched while using the lower resist film as a mask, wherein in the step of etching the film-to-be-etched, a hardened layer is formed in a region of the lower resist film fallen between the first opening and each of the second to fifth openings, and the film-to-be-etched is etched while using the hardened layers as a mask, so as to form a contact hole having a rectangular geometry in a plan view in the film-to-be-etched at a position correspondent to the first opening of the lower resist film.
    Type: Application
    Filed: January 16, 2009
    Publication date: August 20, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Kouichi KONISHI
  • Publication number: 20080148202
    Abstract: In a circuit pattern designing method, a distance calculation data is provided to indicate a relation of a shape of a via bundle and an inter-via-bundle distance in which an over-etched portion is generated in a bottom of a via after an etching; and a provisional layout data is provided to contain an arrangement data of vias which form via bundles. A target one of the via bundles in the provisional layout data is set and the shape of the target via bundle is recognized. The inter-via-bundle distance corresponding to the shape of the target via bundle is calculated as an inhibition distance by referring to the distance calculation data; and the inhibition distance is outputted for the target via bundle.
    Type: Application
    Filed: December 12, 2007
    Publication date: June 19, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Kouichi Konishi
  • Publication number: 20060065979
    Abstract: A semiconductor device which is excellent in a contact property between an antireflection film on an Al contained metal film and a conductive plug is provided with good production stability. The semiconductor device includes a semiconductor substrate, an insulating interlayer 101, and a multi-layer structure. The insulating interlayer 101 is formed in the upper portion of the semiconductor substrate. The multi-layer structure is provided on the insulating interlayer 101. A Ti film 105, a TiN film 107, an AlCu film 109, a Ti film 111, a TiN film 113, and an etching adjustment film 115 are sequentially formed in the multi-layer structure. The semiconductor device includes an insulating interlayer 103 and a conductive plug. The insulating interlayer 103 is provided on the insulating interlayer 101 and the multi-layer structure. The conductive plug penetrates the insulating interlayer 103 and the etching adjustment film 115, and an end surface of the conductive plug is located in the TiN film 113.
    Type: Application
    Filed: September 27, 2005
    Publication date: March 30, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Masashige Moritoki, Kouichi Konishi