Patents by Inventor Kouichi Kouzu

Kouichi Kouzu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7653114
    Abstract: A multibeam semiconductor laser diode having: an n-type semiconductor substrate; an n-type clad layer, an active layer, a p-type clad layer and a contact layer; a plurality of partitioning grooves extending from one end to the other end of the substrate and formed from the contact layer to a predetermined depth of the p-type clad layer; a stripe-shaped ridge sandwiched between two separation grooves; an insulating layer covering an area from each side wall of the contact layer of each ridge to an end of the partitioning region via the separation groove; a first electrode formed on a second plane of the substrate; and a second electrode formed in each partitioning region covering an area above the ridge, separation grooves and multilayer semiconductor layers outside the separation grooves, the second electrode being constituted of a lower second electrode layer and an upper second plated layer.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: January 26, 2010
    Assignee: Opnext Japan, Inc.
    Inventors: Yutaka Inoue, Yasuhisa Semba, Susumu Sorimachi, Kouichi Kouzu
  • Publication number: 20080291960
    Abstract: A multibeam semiconductor laser diode having: an n-type semiconductor substrate; an n-type clad layer, an active layer, a p-type clad layer and a contact layer; a plurality of partitioning grooves extending from one end to the other end of the substrate and formed from the contact layer to a predetermined depth of the p-type clad layer; a stripe-shaped ridge sandwiched between two separation grooves; an insulating layer covering an area from each side wall of the contact layer of each ridge to an end of the partitioning region via the separation groove; a first electrode formed on a second plane of the substrate; and a second electrode formed in each partitioning region covering an area above the ridge, separation grooves and multilayer semiconductor layers outside the separation grooves, the second electrode being constituted of a lower second electrode layer and an upper second plated layer.
    Type: Application
    Filed: May 22, 2008
    Publication date: November 27, 2008
    Inventors: Yutaka Inoue, Yasuhisa Semba, Susumu Sorimachi, Kouichi Kouzu