Patents by Inventor Kouichi KUMAKI

Kouichi KUMAKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10151792
    Abstract: A semiconductor device manufacturing method includes forming a plurality of semiconductor chips on a main surface of a semiconductor wafer, electrically testing each of the semiconductor chips, dicing the semiconductor wafer into individual semiconductor chips and assembling each of the semiconductor chips into a package to be a semiconductor device, subjecting the packages to a burn-in test, determining whether each of the semiconductor chips requires the burn-in test to be performed, and generating a determination model for determining whether the semiconductor chips require the burn-in test to be performed.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: December 11, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki Nakamura, Tomoaki Tamura, Kouichi Kumaki
  • Publication number: 20180217203
    Abstract: A semiconductor device manufacturing method includes forming a plurality of semiconductor chips on a main surface of a semiconductor wafer, electrically testing each of the semiconductor chips, dicing the semiconductor wafer into individual semiconductor chips and assembling each of the semiconductor chips into a package to be a semiconductor device, subjecting the packages to a burn-in test, determining whether each of the semiconductor chips requires the burn-in test to be performed, and generating a determination model for determining whether the semiconductor chips require the burn-in test to be performed.
    Type: Application
    Filed: March 23, 2018
    Publication date: August 2, 2018
    Inventors: Yoshiyuki NAKAMURA, Tomoaki TAMURA, Kouichi KUMAKI
  • Patent number: 9945902
    Abstract: A burn-in test process is omitted for some or all lots. In burn-in necessity determination processing, whether each semiconductor chip requires a burn-in test to be performed is determined based on measurement data obtained in a probe test process. In an assembly process, based on the results of determination made in the burn-in necessity determination processing, the assembled packages are sorted into a first lot which includes packages each including a semiconductor chip determined to require a burn-in test to be performed and a second lot which includes packages each including a semiconductor chip determined to require no burn-in test to be performed. In a burn-in test process, only the packages of the first lot are subjected to a burn-in test.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: April 17, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki Nakamura, Tomoaki Tamura, Kouichi Kumaki
  • Publication number: 20150369857
    Abstract: A burn-in test process is omitted for some or all lots. In burn-in necessity determination processing, whether each semiconductor chip requires a burn-in test to be performed is determined based on measurement data obtained in a probe test process. In an assembly process, based on the results of determination made in the burn-in necessity determination processing, the assembled packages are sorted into a first lot which includes packages each including a semiconductor chip determined to require a burn-in test to be performed and a second lot which includes packages each including a semiconductor chip determined to require no burn-in test to be performed. In a burn-in test process, only the packages of the first lot are subjected to a burn-in test.
    Type: Application
    Filed: June 9, 2015
    Publication date: December 24, 2015
    Inventors: Yoshiyuki NAKAMURA, Tomoaki TAMURA, Kouichi KUMAKI