Patents by Inventor Kouichi Meguro
Kouichi Meguro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10347618Abstract: Various embodiments of the present disclosure include a non-volatile memory semiconductor device and a device that uses the same, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present disclosure, it is possible to provide a high-quality semiconductor device, in which downsizing and cost reduction can be realized.Type: GrantFiled: November 21, 2017Date of Patent: July 9, 2019Assignee: VALLEY DEVICE MANAGEMENTInventors: Masanori Onodera, Kouichi Meguro, Junji Tanaka
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Publication number: 20180076188Abstract: Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized.Type: ApplicationFiled: November 21, 2017Publication date: March 15, 2018Inventors: Masanori Onodera, Kouichi Meguro, Junji Tanaka
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Patent number: 9837397Abstract: Various embodiments of the present disclosure include a non-volatile memory semiconductor device and a device that uses the same, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present disclosure, it is possible to provide a high-quality semiconductor device, in which downsizing and cost reduction can be realized.Type: GrantFiled: October 13, 2016Date of Patent: December 5, 2017Assignee: VALLEY DEVICE MANAGEMENTInventors: Masanori Onodera, Kouichi Meguro, Junji Tanaka
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Publication number: 20170069614Abstract: Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized.Type: ApplicationFiled: October 13, 2016Publication date: March 9, 2017Inventors: Masanori Onodera, Kouichi Meguro, Junji Tanaka
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Patent number: 9472540Abstract: Various embodiments of the present invention include a method for making a semiconductor device the method including disposing a first semiconductor chip on a first surface of a first substrate, the first substrate comprising a second surface opposing the first surface, depositing a first resin above the first semiconductor chip, disposing a built-in semiconductor device on the first resin. The built-in semiconductor device including a second substrate, a second semiconductor chip disposed on the second substrate, and a second resin that seals the second semiconductor chip. The method including depositing a third resin above the built-in semiconductor device and the first resin and covering a side surface of the first substrate and not extending beyond the second surface of the first substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device fabrication method, in which downsizing and cost reduction can be realized.Type: GrantFiled: May 19, 2015Date of Patent: October 18, 2016Assignee: VALLEY DEVICE MANAGEMENTInventors: Masanori Onodera, Kouichi Meguro, Junji Tanaka
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Patent number: 9443827Abstract: A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of the first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar electrode being exposed on the resin section and at least a part of the side surface of the columnar electrode being covered; and a bonding wire connecting the pad electrode and the columnar electrode with a part of the bonding wire being embedded in the columnar electrode as one end of the bonding wire being exposed on the lower surface of the columnar electrode and the remaining part of the bonding wire being covered with the resin section, and a method for manufacturing the same.Type: GrantFiled: October 22, 2014Date of Patent: September 13, 2016Assignee: Cypress Semiconductor CorporationInventor: Kouichi Meguro
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Patent number: 9368424Abstract: A method of fabricating a semiconductor device includes the steps of providing a heat-resistant sheet on an interposer so as to cover electrode terminals provided on the interposer, and sealing a semiconductor chip on the interposer sandwiched between molds with a sealing material. The electrode terminals are covered by the heat-resistant resin for protection, and the semiconductor chip is then sealed with resin. It is thus possible to avoid the problem in which contaminations adhere to the electrode terminals. This makes it possible to prevent the occurrence of resin burrs on the interposer and contamination of the electrode pads and to improve the production yield.Type: GrantFiled: May 20, 2005Date of Patent: June 14, 2016Assignee: Cypress Semiconductor CorporationInventors: Yasuhiro Shinma, Junichi Kasai, Kouichi Meguro, Masanori Onodera, Junji Tanaka
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Patent number: 9293441Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.Type: GrantFiled: October 4, 2011Date of Patent: March 22, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Masataka Hoshino, Junichi Kasai, Kouichi Meguro, Ryota Fukuyama, Yasuhiro Shinma, Koji Taya, Masanori Onodera, Naomi Masuda
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Patent number: 9142440Abstract: A method of producing a carrier structure for fabricating a stacked-type semiconductor device includes laminating thin plates for a lower carrier associated with an upper carrier. The method includes forming openings in the thin plates by etching or electric discharge machining. The lower carrier includes a magnet that is buried therein and the magnet maintains contact between the lower carrier and the upper carrier. A thin plate of the laminated thin plates is provided on each opposing surface of the magnet. The lower carrier further includes multiple magnets arranged around a periphery of the lower carrier and through a center region of the lower carrier that is between magnets on the periphery.Type: GrantFiled: December 3, 2008Date of Patent: September 22, 2015Assignee: Cypess Semiconductor CorporationInventors: Masanori Onodera, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Koji Taya, Junji Tanaka
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Publication number: 20150255446Abstract: Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized.Type: ApplicationFiled: May 19, 2015Publication date: September 10, 2015Inventors: Masanori Onodera, Kouichi Meguro, Junji Tanaka
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Patent number: 9041177Abstract: Various embodiments of the present invention include a semiconductor device, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device, in which downsizing and cost reduction can be realized.Type: GrantFiled: December 11, 2012Date of Patent: May 26, 2015Assignee: VALLEY DEVICE MANAGEMENTInventors: Masanori Onodera, Kouichi Meguro, Junji Tanaka
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Publication number: 20150041976Abstract: A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of die first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar electrode being exposed on the resin section and at least a part of the side surface of the columnar electrode being covered; and a bonding wire connecting the pad electrode and the columnar electrode with a part of the bonding wire being embedded in the columnar electrode as one end of the bonding wire being exposed on the lower surface of the columnar electrode and the remaining part of the bonding wire being covered with the resin section, and a method for manufacturing the same.Type: ApplicationFiled: October 22, 2014Publication date: February 12, 2015Inventor: Kouichi MEGURO
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Patent number: 8900993Abstract: A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of die first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar electrode being exposed on the resin section and at least a part of the side surface of the columnar electrode being covered; and a bonding wire connecting the pad electrode and the columnar electrode with a part of the bonding wire being embedded in the columnar electrode as one end of the bonding wire being exposed on the lower surface of the columnar electrode and the remaining part of the bonding wire being covered with the resin section, and a method for manufacturing the same.Type: GrantFiled: March 21, 2011Date of Patent: December 2, 2014Assignee: Spansion LLCInventor: Kouichi Meguro
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Patent number: 8772953Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.Type: GrantFiled: March 13, 2009Date of Patent: July 8, 2014Assignee: Spansion LLCInventors: Koji Taya, Masanori Onodera, Junji Tanaka, Kouichi Meguro
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Patent number: 8586412Abstract: A semiconductor device which includes a first semiconductor chip, a second semiconductor chip flip-chip bonded to the first semiconductor chip, a resin portion for sealing the first semiconductor chip and the second semiconductor chip such that a lower surface of the first semiconductor chip and an upper surface of the second semiconductor chip are exposed and a side surface of the first semiconductor chip is covered, and a post electrode which pierces the resin portion and is connected to the first semiconductor chip, and a manufacturing method thereof are provided.Type: GrantFiled: June 19, 2013Date of Patent: November 19, 2013Assignee: Spansion LLCInventors: Kouichi Meguro, Masanori Onodera
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Publication number: 20130288430Abstract: A semiconductor device which includes a first semiconductor chip, a second semiconductor chip flip-chip bonded to the first semiconductor chip, a resin portion for sealing the first semiconductor chip and the second semiconductor chip such that a lower surface of the first semiconductor chip and an upper surface of the second semiconductor chip are exposed and a side surface of the first semiconductor chip is covered, and a post electrode which pierces the resin portion and is connected to the first semiconductor chip, and a manufacturing method thereof are provided.Type: ApplicationFiled: June 19, 2013Publication date: October 31, 2013Inventors: Kouichi MEGURO, Masanori ONODERA
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Patent number: 8530282Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.Type: GrantFiled: October 7, 2010Date of Patent: September 10, 2013Assignee: Spansion LLCInventors: Koji Taya, Masanori Onodera, Junji Tanaka, Kouichi Meguro
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Patent number: 8492890Abstract: A semiconductor device which includes a first semiconductor chip, a second semiconductor chip flip-chip bonded to the first semiconductor chip, a resin portion for sealing the first semiconductor chip and the second semiconductor chip such that a lower surface of the first semiconductor chip and an upper surface of the second semiconductor chip are exposed and a side surface of the first semiconductor chip is covered, and a post electrode which pierces the resin portion and is connected to the first semiconductor chip, and a manufacturing method thereof are provided.Type: GrantFiled: March 17, 2008Date of Patent: July 23, 2013Assignee: Spansion LLCInventors: Kouichi Meguro, Masanori Onodera
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Patent number: 8481366Abstract: A semiconductor device is provided that includes a semiconductor chip and a resin section that molds the semiconductor chip and has a first through-hole. A through electrode that is electrically coupled to the semiconductor chip, extends through the resin section, and extends between a top edge and a bottom edge of an inner surface of the first through-hole. A cavity which extends between planes corresponding to an upper surface and a lower surface of the resin section is formed inside the first through-hole.Type: GrantFiled: April 26, 2011Date of Patent: July 9, 2013Assignee: Spansion LLCInventors: Masahiko Harayama, Kouichi Meguro, Junichi Kasai
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Patent number: 8466552Abstract: A manufacturing method of a semiconductor device includes: forming a columnar electrode on a semiconductor wafer; flip-chip bonding a second semiconductor chip onto the semiconductor wafer; forming a molding portion on the semiconductor wafer, the molding portion covering and molding the columnar electrode and the second semiconductor chip; grinding or polishing the molding portion and the second semiconductor chip so that an upper face of the columnar electrode and an upper face of the semiconductor chip are exposed; and cutting the molding portion and the semiconductor wafer so that a first semiconductor chip, where the second semiconductor chip is flip-chip bonded and the columnar electrode is formed, is formed.Type: GrantFiled: June 21, 2011Date of Patent: June 18, 2013Assignee: Spansion LLCInventors: Masanori Onodera, Kouichi Meguro