Abstract: A phase adjuster arranges phases of waveforms of a complex signal after orthogonal transform. An edge detector detects an edge of the complex signal after phase adjustment. A phase shift detector detects phase shift of an output signal of the edge detector between the in-phase signal and the quadrature signal after the orthogonal transform, and outputs a phase error signal (PE). The oscillator connected to mixers and a shifter to perform the orthogonal transform includes a phase adjustment section adjusting an edge of a voltage controlled oscillator (VCO) clock based on the phase error signal (PE) and correcting the phase shift of an original signal.

Abstract: A phase adjuster arranges phases of waveforms of a complex signal after orthogonal transform. An edge detector detects an edge of the complex signal after phase adjustment. A phase shift detector detects phase shift of an output signal of the edge detector between the in-phase signal and the quadrature signal after the orthogonal transform, and outputs a phase error signal (PE). The oscillator connected to mixers and a shifter to perform the orthogonal transform includes a phase adjustment section adjusting an edge of a voltage controlled oscillator (VCO) clock based on the phase error signal (PE) and correcting the phase shift of an original signal.

Abstract: An analog complex filter combines an in-phase signal and a quadrature signal to output first and second analog signals. An analog-to-digital converter converts the first and second analog signals into first and second digital signals. A first digital complex filter attenuates a component corresponding to the quadrature signal of the first digital signal and outputs the resultant signal as a third digital signal, and attenuates a component corresponding to the in-phase signal of the second digital signal and outputs the resultant signal as a fourth digital signal. An IQ imbalance correction circuit corrects a quadrature error and an amplitude error between the third and fourth digital signals.

Abstract: An analog complex filter combines an in-phase signal and a quadrature signal to output first and second analog signals. An analog-to-digital converter converts the first and second analog signals into first and second digital signals. A digital complex filter attenuates components corresponding to the quadrature signal and the in-phase signal of the first and second digital signals, respectively. A digital bandwidth limited filter allows a target component and an image component contained in the digital complex signal composed of the first and second digital signals from the digital complex filter to pass therethrough, and attenuates an adjacent interference component. An IQ imbalance correction circuit corrects a quadrature error and an amplitude error between the first and second digital signals from the digital band-pass filter.

Abstract: An analog complex filter combines an in-phase signal and a quadrature signal to output first and second analog signals. An analog-to-digital converter converts the first and second analog signals into first and second digital signals. A digital complex filter attenuates components corresponding to the quadrature signal and the in-phase signal of the first and second digital signals, respectively. A digital bandwidth limited filter allows a target component and an image component contained in the digital complex signal composed of the first and second digital signals from the digital complex filter to pass therethrough, and attenuates an adjacent interference component. An IQ imbalance correction circuit corrects a quadrature error and an amplitude error between the first and second digital signals from the digital band-pass filter.

Abstract: An analog complex filter combines an in-phase signal and a quadrature signal to output first and second analog signals. An analog-to-digital converter converts the first and second analog signals into first and second digital signals. A first digital complex filter attenuates a component corresponding to the quadrature signal of the first digital signal and outputs the resultant signal as a third digital signal, and attenuates a component corresponding to the in-phase signal of the second digital signal and outputs the resultant signal as a fourth digital signal. An IQ imbalance correction circuit corrects a quadrature error and an amplitude error between the third and fourth digital signals.

Abstract: A plurality of comparators (CMP1, CMP2, . . . ) respectively correspond to a plurality of reference voltages (V1, V2, . . . ), and each compares a reference voltage corresponding to the comparator with a signal level of an analog signal (Sin). An encoder (102) generates a digital signal (De) corresponding to the analog signal (Sin) based on outputs (S1, S2, . . . ) of the plurality of comparators. A pattern detection circuit (103) detects that a temporal change of an output (S3) of a first comparator matches a predetermined first particular pattern. A control circuit (104) corrects a digital value of the digital signal (De) in response to detection by the pattern detection circuit. The temporal change of the output (S3) of the first comparator becomes the first particular pattern when an amplitude of the analog signal (Sin) is smaller than a predetermined amplitude.

Abstract: A semiconductor device comprises an overflow detection circuit (5) which compares an output of at least one integrator in a ?? modulator (13) with a predetermined value to output an overflow detection signal; an overflow frequency calculation circuit (6) which calculates an overflow frequency value that is the frequency of the output from the integrator being outside a normal range, based on the overflow detection signal, and outputs the overflow frequency value; an oscillation judgment circuit (7) which judges whether the ?? modulator (13) is in the oscillation state or not based on the overflow frequency value; and an oscillation halt circuit which suppresses oscillation of the ?? modulator (13) when the oscillation judgment circuit (7) judges that the ?? modulator is in the oscillation state; wherein it is determined whether the output of the integrator is temporarily outside the normal range due to noise or the like or the output of the integrator is outside the normal range due to oscillation, by obtaini

Abstract: A plurality of comparators (CMP1, CMP2, . . . ) respectively correspond to a plurality of reference voltages (V1, V2, . . . ), and each compares a reference voltage corresponding to the comparator-with a signal level of an analog signal (Sin). An encoder (102) generates a digital signal (De) corresponding to the analog signal (Sin) based on outputs (S1, S2, . . . ) of the plurality of comparators. A pattern detection circuit (103) detects that a temporal change of an output (S3) of a first comparator matches a predetermined first particular pattern. A control circuit (104) corrects a digital value of the digital signal (De) in response to detection by the pattern detection circuit. The temporal change of the output (S3) of the first comparator becomes the first particular pattern when an amplitude of the analog signal (Sin) is smaller than a predetermined amplitude.

Abstract: A semiconductor device comprises an overflow detection circuit (5) which compares an output of at least one integrator in a ?? modulator (13) with a predetermined value to output an overflow detection signal; an overflow frequency calculation circuit (6) which calculates an overflow frequency value that is the frequency of the output from the integrator being outside a normal range, based on the overflow detection signal, and outputs the overflow frequency value; an oscillation judgment circuit (7) which judges whether the ?? modulator (13) is in the oscillation state or not based on the overflow frequency value; and an oscillation halt circuit which suppresses oscillation of the ?? modulator (13) when the oscillation judgment circuit (7) judges that the ?? modulator is in the oscillation state; wherein it is determined whether the output of the integrator is temporarily outside the normal range due to noise or the like or the output of the integrator is outside the normal range due to oscillation, by obtaini

Abstract: A conventional multi-input adder has a problem that only either the number of stages of operation blocks or the number of half adders and full adders can be reduced. In order to solve the problem of the prior art, half adders (HA201, HA203, HA204, HA202, HA205) are used only in a position at a lower digit having two inputs in an operation block (2a), a position having five inputs and two carries from the lower digit in a stage three stages prior to a final-stage operation block (2d), and a position one stage prior to the final-stage operation block (2d).

Abstract: Conventional multi-input multiplication and addition circuit having fixed multipliers has problems in that when the number of inputs increases, the number of partial product generator circuits would increase, and also the number of stages of the addition blocks would increase. In order to solve the above-described problems, it is constructed such that there are provided a multi-input encoder (11) which comprises a plurality of encoder parts (11a) each of which accomplishes a function corresponding to generation of a partial product in multiplication, and which also has a plurality of outputs which correspond to the multi-bit output of the respective encoder parts, and a multi-input adder circuit (12) which adds the plural outputs from the multi-input encoder (11).

Abstract: The conventional two's complement multiplier which is constituted by a Booth encoder, a partial production generation circuit, and an adder has a problem that the circuit scale would be increased because a bit extension is performed when the multiplier is adapted to an unsigned multiplication. A multiplication circuit of the present invention is provided with a first Booth encoder (1) for encoding lower-order several bits of a multiplier according to first rules of encoding using a Booth algorithm, and a second Booth encoder (5) for encoding most-significant several bits of the multiplier according to second rules of encoding using a Booth algorithm, which are different from the first rules of encoding, and thereby the most-significant several bits of the multiplier are encoded using the Booth algorithm which is different from that for the lower-order several bits.

Abstract: Conventional signal write correction circuits involve a problem that when n-phase clock is selected, the waveform may be distorted in high speed operation if the last-phase clock is selected. Two delay selection circuits (16a, 16b) select the odd-numbered edges and the even-numbered edges of a multipulse signal used for write correction. To select the edges, each of the delay selection circuits (16a, 16b) uses two enable signals. The exclusive OR of the outputs of the two delay selection circuits (16a, 16b) is taken to generate the timing of the multipulse signal.

Abstract: There has been an issue that the operation of a semiconductor circuit performing edge timing control cannot follow up in the multipulse generation process where high multiplication of speed progresses every year. A light strategy drive comprises a control register (22) storing timing edge information for generating the edge of a recording waveform signal, a PLL (23) generating a clock for generating the edge of a recording waveform signal, and a timing control circuit (24) for receiving timing edge information corresponding to the recording waveform signal from the control register (22) to output timing edge information having a predetermined amount of delay in parallel and compounding the edges based on the timing edge information outputted in parallel. Timing edge can be controlled with high precision even at the time of high speed operation, and a high precision multipulse can be generated.

Abstract: A write correction circuit (100) includes, in its input stage, a pulse modification circuit (11) for removing patterns (sections) included in a write pulse signal (s1), which patterns have lengths outside a range that is previously determined as a section length of the write pulse signal, and outputting a modified pulse signal (s1) that is obtained by modifying the waveform of the write pulse signal, and write correction is performed to the modified pulse signal (s11) that is obtained in the pulse modification circuit (11). Thereby, highly precise write correction can be performed to the write pulse signal (s1) inputted to the write correction circuit (100).

Abstract: To perform gain adjustment of the amplitude of a binary phase shift keying (BPSK) wobble signal from a DVD to enable high-precision demodulation of address information, a peak detection circuit detects a peak value in a time period equal to or more than a half period of the input wobble signal. A gain computation circuit computes a gain adjustment coefficient from the peak value. The gain adjustment coefficient is limited to within a fixed range by a limiter and then supplied to a multiplier. To adjust digital-related delay generated when the gain adjustment coefficient is computed, the input wobble signal is delayed by a delay circuit before being supplied to the multiplier. The multiplier multiplies the wobble signal from the delay circuit by the gain adjustment coefficient and outputs the result as the digital AGC output.

Abstract: A path storing circuit has path holding parts at a plurality of stages storing a survivor path and corresponding to times. A majority decision circuit receives output values of three delay circuits including the top and bottom delay circuits each receiving a selected output of a selector out of six delay circuits in the path holding part at the final stage and makes a decision by a majority.

Abstract: A phase adjustment circuit includes: a carrier-wave-delay adjusting circuit for delaying an input carrier wave and outputting the delayed carrier wave, in accordance with phase information; and a phase-difference detecting/adjusting circuit for detecting a phase difference between an input signal and the delayed carrier wave, outputting, as the phase information, a value according to the detected phase difference, adjusting the delayed carrier wave such that the delayed carrier wave has a phase substantially coincident with a phase of the input signal, and outputting the resultant carrier wave as a phase-adjusted carrier wave. In a steady state, the phase-difference detecting/adjusting circuit outputs, as the phase information, a value indicating the presence of a phase difference.

Abstract: A waveform equalizer, which has a partial response characteristic represented in the form of PR (a, b, c, b, a) which is a quaternary transfer function characteristic, is made up an analog filter, an ADC (analog/digital converter), and an FIR filter, for providing matching with the frequency characteristic of a read back waveform read from a recording medium. Such signal processor characteristic approximation to the regenerative signal characteristic makes it possible to easily achieve equalization without particularly emphasizing the regenerative signal, thereby achieving a reduced circuit scale.