Patents by Inventor Kouichi Nagasawa
Kouichi Nagasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5122857Abstract: A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM further has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring being formed from the same layer as that for forming the second word lines.Type: GrantFiled: January 8, 1991Date of Patent: June 16, 1992Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Katsuro Sasaki, Kouichi Nagasawa, Satoshi Meguro
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Patent number: 5055420Abstract: After contact holes for the P- and N-type source or drain regions of P- and N-channel MOSFETs have been made at a common step, an N-type impurity is ion-implanted into at least the N-type source or drain regions through the contact holes. The N-type impurity is annealed to fornm an N-type region which is deeper than the N-type source or drain regions. During the annealing treatment, the N-type source or drain regions are covered with an insulating film.Type: GrantFiled: May 9, 1989Date of Patent: October 8, 1991Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Kouichi Nagasawa, Makoto Motoyoshi, Kiyoshi Nagai, Satoshi Meguro
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Patent number: 5028975Abstract: Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, the electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.Type: GrantFiled: May 23, 1990Date of Patent: July 2, 1991Assignee: Hitachi, Ltd.Inventors: Kouichi Nagasawa, Yoshio Sakai, Osamu Minato, Toshiaki Masuhara, Satoshi Meguro
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Patent number: 5005068Abstract: A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring being formed from the same layer as that for forming the second word lines.Type: GrantFiled: July 7, 1989Date of Patent: April 2, 1991Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Katsuro Sasaki, Kouichi Nagasawa, Satoshi Meguro
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Patent number: 4990998Abstract: A semiconductor device includes a first conductor layer into which is diffused an impurity for lowering the resistance, and a second conductor layer provided on the upper side of the first conductor layer through a stopper layer which suppresses the out-diffusion of the impurity. By virtue of the existence of the stopper layer, it is possible to inhibit the above-described impurity from being diffused into the second conductor layer. In SRAM, resistance variations between high-resistance elements which correspond to the second conductor layer can be suppressed, so that it is possible to prevent the lowering of the yield with respect to the electrical reliability. In SRAM, further, the resistance of the high-resistance elements is not lowered; therefore, it is possible to reduce the power consumption.Type: GrantFiled: February 7, 1989Date of Patent: February 5, 1991Assignee: Hitachi, Ltd.Inventors: Atsuyoshi Koike, Shuji Ikeda, Kouichi Nagasawa
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Patent number: 4912674Abstract: A mask-programmed ROM includes depletion type load MOSFETs provided between data lines in a memory array and a power supply voltage, the MOSFETs having a ground potential of the circuit applied to their gates. Reading of data is carried out by an amplifying MOSFET which supplies a current to a selected data line through a depletion type MOSFET which is supplied at its gate with the circuit ground potential. Thus, bias voltages which are respectively applied to the data lines and a sense amplifier which receives a signal read out from a selected data line are made equal to each other, thereby achieving a high-speed read operation.Type: GrantFiled: February 14, 1989Date of Patent: March 27, 1990Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Youichi Matsumoto, Ryuuji Shibata, Isamu Kobayashi, Satoshi Meguro, Kouichi Nagasawa, Hideo Meguro, Hisahiro Moriuchi, Masahiro Ogata, Kikuo Sakai, Toshifumi Takeda
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Patent number: 4890148Abstract: A static RAM exhibiting a high reliability and suited to a higher density of integration is disclosed. In each memory cell of this static RAM, the cross coupling of a flip-flop circuit is made by gate electrodes of MISFETs constituting this flip-flop circuit. In addition, a source line is formed by the same step as that of a word line. A resistance value of a polycrystalline silicon layer which is a load resistor is changed in accordance with information to be stored. Furthermore, semiconductor regions for preventing soft errors attributed to alpha particles etc. are formed under the MISFETs constituting the flip-flop circuit, so that the channels are not adversely affected.Type: GrantFiled: July 7, 1988Date of Patent: December 26, 1989Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Kouichi Nagasawa, Satoshi Meguro, Sho Yamamoto
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Patent number: 4805143Abstract: A mask-programmed ROM includes depletion type load MOSFETs provided between data lines in a memory array and a power supply voltage, the MOSFETs having a ground potential of the circuit applied to their gates. Reading of data is carried out by an amplifying MOSFET which supplies a current to a selected data line through a depletion type MOSFET which is supplied at its gate with the circuit ground potential. Thus, bias voltages which are respectively applied to the data lines and a sense amplifier which receives a signal read out from a selected data line are made equal to each other, thereby achieving a high-speed read operation.Type: GrantFiled: January 12, 1987Date of Patent: February 14, 1989Assignees: Hitachi Ltd., Hitachi VLSI Engineering Corp.Inventors: Youichi Matsumoto, Ryuuji Shibata, Isamu Kobayashi, Satoshi Meguro, Kouichi Nagasawa, Hideo Meguro, Hisahiro Moriuchi, Masahiro Ogata, Kikuo Sakai, Toshifumi Takeda
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Patent number: 4803534Abstract: A semiconductor device includes a first conductor layer into which is diffused an impurity for lowering the resistance, and a second conductor layer provided on the upper side of the first conductor layer through a stopper layer which suppresses out-diffusion of the impurity. By virtue of the existence of the stopper layer, it is possible to inhibit the above-described impurity from being diffused into the second conductor layer. In a SRAM, resistance variations between high-resistance elements which correspond to the second conductor layer can be suppressed, so that it is possible to prevent lowering of the yield with respect to the electrical reliability. In a SRAM, further, the resistance of the high-resistance elements is not lowered; therefore, it is possible to reduce the power consumption.Type: GrantFiled: June 18, 1986Date of Patent: February 7, 1989Assignee: Hitachi, Ltd.Inventors: Atsuyoshi Koike, Shuji Ikeda, Kouichi Nagasawa
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Patent number: 4792841Abstract: Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after the polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.Type: GrantFiled: July 24, 1984Date of Patent: December 20, 1988Assignee: Hitachi, Ltd.Inventors: Kouichi Nagasawa, Yoshio Sakai, Osamu Minato, Toshiaki Masuhara, Satoshi Meguro
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Patent number: 4734383Abstract: After contact holes for the P- and N-type source or drain regions of P- and N-channel MOSFETs have been made at a common step, an N-type impurity is ion-implanted into at least the N-type source or drain regions through the contact holes. The N-type impurity is annealed to form an N-type region which is deeper than the N-type source or drain regions. During the annealing treatment, the N-type source or drain regions are covered with an insulating film.Type: GrantFiled: November 22, 1985Date of Patent: March 29, 1988Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Kouichi Nagasawa, Makoto Motoyoshi, Kiyoshi Nagai, Satoshi Meguro
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Patent number: 4637124Abstract: Herein disclosed is a process for fabricating a semiconductor integrated circuit device which is provided with N-channel and P-channel MISFETs each having a pair of side wall spacers formed simultaneously at both the sides of a gate electrode thereof. The P-channel MISFET has its source and drain regions formed by a boron ion implantation using the gate electrode and the paired side wall spacers as a mask. The boron having a high diffusion velocity is suppressed from diffusing below the gate electrode.Type: GrantFiled: March 18, 1985Date of Patent: January 20, 1987Assignee: Hitachi, Ltd.Inventors: Kousuke Okuyama, Norio Suzuki, Satoshi Meguro, Kouichi Nagasawa
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Patent number: 4626450Abstract: A process for producing semiconductor devices having excellent electric characteristics such as high threshold voltage Vth and small leakage current, maintaining high yields while preventing the occurrence of thermal etching at the time of heat-treatment to form a well diffusion layer in semiconductor devices such as CMOS IC's. Namely, a semiconductor wafer having a silicon dioxide film formed on the main surface thereof is heat-treated at a high temperature in an inert gas atmosphere. In this case, oxygen is contained in small amounts in the inert gas, so that pinholes formed in the silicon dioxide film are buried therein by the action of oxygen gas. Therefore, thermal etching is not generated by the high temperature inert gas, and the yields of semiconductor devices can be increased.Type: GrantFiled: June 24, 1985Date of Patent: December 2, 1986Assignee: Hitachi, Ltd.Inventors: Akihiko Tani, Takashi Aoyagi, Shuji Ikeda, Kouichi Nagasawa
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Patent number: 4549340Abstract: Disclosed is a method of manufacturing a semiconductor device which includes MOSFETs of the two-channel conductivity types of P- and N-channel types on a single semiconductor substrate. According to the present invention, a first mask and a second mask are used. The first mask covers that surface part of the semiconductor substrate in which the P-channel type MOSFET is to be formed, and it serves as a mask when an N-type impurity is introduced into the semiconductor substrate. The first mask has a property and etching rate different from those of a film formed by the thermal oxidation of the semiconductor substrate surface. The second mask covers that surface part of the semiconductor substrate which has been formed with the N-channel type MOSFET, and it serves as a mask when a P-type impurity is introduced into the semiconductor substrate. The second mask is used as an inter-layer insulator film.Type: GrantFiled: September 8, 1983Date of Patent: October 29, 1985Assignee: Hitachi, Ltd.Inventors: Kouichi Nagasawa, Shuji Ikeda, Norio Suzuki, Yoshio Sakai
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Patent number: 4243897Abstract: The single input gate electrode in a conventional CCD shift register is replaced by four spaced electrodes. The fourth electrode adjacent to the first transfer electrode has an area larger than that of the second electrode which always has a DC voltage applied thereto. Three driving pulses are applied in a predetermined sequence to the first, third and fourth electrodes while the two bit values of 2-bit information are written into the register and a charge is accumulated directly under the fourth input gate electrode at one of four levels as determined by the combination of the write bit values. Then the accumulated charge is stepwise transferred in the same manner as in conventional CCD shift registers.Type: GrantFiled: April 28, 1978Date of Patent: January 6, 1981Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuyasu Fujishima, Michihiro Yamada, Kouichi Nagasawa
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Patent number: 4110899Abstract: Method for manufacturing complementary insulated gate field effect transistors of LOCOS (local oxidation of silicon) structure wherein after the formation of a well layer, an impurity having higher doping level than and the same conductivity type as a semiconductor substrate (well layer) is ion implanted at an area in the semiconductor substrate on which a field oxide layer is to be formed using a silicon nitride layer as a mask, and the semiconductor substrate surface is selectively thermally oxidized using the silicon nitride layer as a mask.Type: GrantFiled: January 4, 1977Date of Patent: September 5, 1978Assignee: Hitachi, Ltd.Inventors: Kouichi Nagasawa, Yasunobu Kosa, Satoshi Meguro
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Patent number: RE31079Abstract: Method for manufacturing .Iadd.semiconductor devices including, e.g., .Iaddend.complementary insulated gate field effect transistors of LOCOS (local oxidation of silicon) structure wherein after the formation of a well layer, an impurity having higher doping level than and the same conductivity type as a semiconductor substrate (well layer) is ion implanted at an area in the semiconductor substrate on which a field oxide layer is to be formed using .Iadd.an oxidation-resistive material, e.g. .Iaddend.a silicon nitride layer.Iadd., .Iaddend.as a mask, and the semiconductor substrate surface is selectively thermally oxidized using the silicon nitride layer as a mask.Type: GrantFiled: August 29, 1980Date of Patent: November 16, 1982Assignee: Hitachi, Ltd.Inventors: Kouichi Nagasawa, Yasunobu Kosa, Satoshi Meguro