Abstract: A disturb mode control circuit designates a disturb mode for activating an internal cycle setting circuit in response to a predetermined state of an address signal at a terminal when a disturb mode designating signal applied from a control circuit is active. The activated internal cycle setting circuit continuously issues a clock signal having a predetermined period to the control circuit. In accordance with the mode detection signal applied from the disturb mode control circuit and the clock signal applied from the internal cycle setting circuit, the control circuit successively generates an internal address signal in synchronization with the clock signal applied from an internal address generating circuit for selecting the word line in a memory cell array.

Abstract: An output circuit for providing data read from a memory cell is disclosed. When a power source is turned on, initial value data set in a register circuit is read and then latched in comparison circuits. The data latched in the comparison circuits are applied through NOR circuits to a plurality of transistors, so that the transistors corresponding in number to the initial value data are rendered conductive. An output signal is fed back from a common output terminal of the respective transistors to the comparison circuits, so that the respective comparison circuits compare between respective threshold values and the output signal. Thus, a determination is made as to whether the gradient of leading edges of waveforms of the output signal is sharp or gradual. If the gradient is gradual, the number of transistors becoming conductive increases, whereas if the gradient is sharp, the number of such transistors decreases.