Patents by Inventor Kouichi Ookawa

Kouichi Ookawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7193430
    Abstract: There is provided a semiconductor integrated circuit device with a filer circuit serving for eliminating a glitch contained in a logic signal supplied to the device, wherein the filter circuit includes: a first delay circuit activated within a certain period after each rising edge timing of input logic signals to delay the rising edge; a second delay circuit activated within a certain period after each falling edge timing of the input logic signals to delay the falling edge; and an output driver controlled by outputs of the first and second delay circuits to output delayed logic signals to an output node in response to the input logic signals.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: March 20, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kouichi Ookawa
  • Publication number: 20050088224
    Abstract: There is provided a semiconductor integrated circuit device with a filer circuit serving for eliminating a glitch contained in a logic signal supplied to the device, wherein the filter circuit includes: a first delay circuit activated within a certain period after each rising edge timing of input logic signals to delay the rising edge; a second delay circuit activated within a certain period after each falling edge timing of the input logic signals to delay the falling edge; and an output driver controlled by outputs of the first and second delay circuits to output delayed logic signals to an output node in response to the input logic signals.
    Type: Application
    Filed: June 14, 2004
    Publication date: April 28, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kouichi Ookawa