Patents by Inventor Kouichi Shimoda

Kouichi Shimoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6756269
    Abstract: A patterning of a first poly-silicon is processed, to divide the first poly-silicon into memory elements and expose silicon substrate portions which function as boundaries. A second poly-silicon is formed on the silicon substrate. A first N+ impurity diffusing region is formed by diffusing impurities included in the second poly-silicon into the silicon substrate at the boundary via heat-treatment. Then, using the first and second poly-silicon as a material of a floating gate, forming a material of an intermediate insulating film on this material, and forming a material of a control gate on the insulating film, a control gate and a floating gate are formed by etching these materials. Finally, a second impurity diffusing region is formed in the silicon substrate, the second impurity diffusing region being connected with the first impurity diffusing region.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: June 29, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kouichi Shimoda
  • Publication number: 20040014282
    Abstract: A patterning of a first poly-silicon (4) is processed, to divide the first poly-silicon into each memory element and expose silicon substrate (1) portions which comprise boundary. A second poly-silicon (4′) is formed on silicon substrate (1) And, a first N+ impurity diffusing region (14) is formed by diffusing impurity, which is included in the second poly-silicon (4′), into the silicon substrate (1) at the boundary portion with heat-treatment. After this, using the first poly-silicon and the second poly-silicon as a material of a floating gate, forming a material of an intermediate insulating film (5) on this material, and forming a material of a control gate on this material, a control gate and a floating gate are formed by etching these materials. Finally, a second impurity diffusing region, is formed in the silicon substrate (1), and this second impurity diffusing region (12′) is connected with the first impurity diffusing region (14).
    Type: Application
    Filed: April 11, 2003
    Publication date: January 22, 2004
    Inventor: Kouichi Shimoda
  • Patent number: 5171698
    Abstract: The method of fabricating a MOS transistor comprises the steps of successively forming a polycrystalline silicon film and a first silicon oxide film on a semiconductor substrate, forming a silicon nitride film on the first silicon oxide film on an element region, converting the polycrystalline silicon film on an element separation region into a second silicon oxide film, forming a second silicon oxide film on the side of the polycrystalline silicon film in the element region, forming a channel stopper layer underneath the element separation region of the semiconductor substrate, forming a third oxide film on the element separation region of the semiconductor substrate, and removing selectively the polycrystalline silicon, first silicon oxide film and the silicon nitride film to form a gate electrode forming region of the MOS transistor region.
    Type: Grant
    Filed: April 8, 1992
    Date of Patent: December 15, 1992
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kouichi Shimoda
  • Patent number: 5100815
    Abstract: To create bipolar and MOS transistors, a substrate is covered with polysilicon. The polysilicon is patterned to form gate electrodes in MOS transistor regions, and to form polysilicon patterns surrounding central openings in bipolar transistor base-and-emitter regions. Lightly-doped source and drain layers are created by implanting impurities into the MOS transistor regions, using the gate electrodes as masks. Active bases are formed in the base-and-emitter regions below the central openings. Then sidewalls are added to the polysilicon, narrowing the central openings and widening the gate electrodes. Impurities are implanted into the MOS transistor regions, using the widened gate electrodes as masks, to create heavily-doped source and drain layers. The active base areas are doped below the narrowed central openings to create emitters.
    Type: Grant
    Filed: December 27, 1990
    Date of Patent: March 31, 1992
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Ko Tsubone, Yoshio Umemura, Kouichi Shimoda