Abstract: A semiconductor device includes a semiconductor substrate having an insulation layer and a semiconductor layer formed on the insulation layer; a channel area formed in the semiconductor layer; a gate electrode formed on the channel area; a source area formed in the semiconductor layer and having a depth not reaching the insulation layer; a drain area formed in the semiconductor layer adjacent to the source area with the channel area in between and having a depth reaching the insulation layer; a separation area disposed next to the source area opposite to the channel area and having a depth not reaching the insulation layer; a high-concentration body area formed in the semiconductor layer at lease in a surface layer thereof and between the first separation area and the second separation area; and a body contact disposed on the high-concentration body area.

Abstract: A semiconductor device includes a semiconductor substrate having an insulation layer and a semiconductor layer formed on the insulation layer; a channel area formed in the semiconductor layer; a gate electrode formed on the channel area; a source area formed in the semiconductor layer and having a depth not reaching the insulation layer; a drain area formed in the semiconductor layer adjacent to the source area with the channel area in between and having a depth reaching the insulation layer; a separation area disposed next to the source area opposite to the channel area and having a depth not reaching the insulation layer; a high-concentration body area formed in the semiconductor layer at lease in a surface layer thereof and between the first separation area and the second separation area; and a body contact disposed on the high-concentration body area.

Abstract: A semiconductor device includes a first transistor having a first gate oxide layer with a first thickness; a second transistor having a second gate oxide layer with a second thickness different from the first thickness; and at least one of a capacitor and a variable capacitance diode. The one of the capacitor and the variable capacitance diode includes a first electrode formed in a first area and a second area, a second electrode formed in the first area with the first gate oxide layer inbetween, and a third electrode formed in the second area with the second gate oxide layer inbetween.

Abstract: A method for fabricating a semiconductor device in which plural transistors including a first transistor and a second transistor are integrated includes a first step for forming the first transistor such that a distance between a drain contact and a gate electrode of the first transistor is a first distance, and a second step for forming the second transistor such that a distance between a drain contact and a gate electrode of the second transistor is a second distance larger than the first distance.

Abstract: A semiconductor device includes a first transistor having a first gate oxide layer with a first thickness; a second transistor having a second gate oxide layer with a second thickness different from the first thickness; and at least one of a capacitor and a variable capacitance diode. One of the capacitor and the variable capacitance diode includes a first electrode having a first area and a second area; a second electrode formed in the first area with the first gate oxide layer in between; and a third electrode formed in the second area with the second gate oxide layer in between. The second electrode and third electrode have comb shapes nested inside one another.

Abstract: A method for manufacturing a semiconductor device in which a plurality of wiring layers are formed includes the steps of (a) preparing a semiconductor device on which a plurality of semiconductor elements are formed on one surface thereof, (b) forming a spiral inductor on the semiconductor substrate astride three or more wiring layers, and (c) forming a circuit wiring other than the spiral inductor in the wiring layer. The step of forming the spiral inductor and the step of forming the circuit wiring are performed simultaneously.

Abstract: A semiconductor device includes a first transistor having a first gate oxide layer with a first thickness; a second transistor having a second gate oxide layer with a second thickness different from the first thickness; and at least one of a capacitor and a variable capacitance diode. One of the capacitor and the variable capacitance diode includes a first electrode having a first area and a second area; a second electrode formed in the first area with the first gate oxide layer in between; and a third electrode formed in the second area with the second gate oxide layer in between. The second electrode and third electrode have comb shapes nested inside one another.

Abstract: A ferroelectric capacitor has a top electrode, a bottom electrode, a ferroelectric body disposed between the top and bottom electrodes, and a dielectric lining disposed below the top electrode and above the bottom electrode, protecting the sides of the ferroelectric body. The ferroelectric body can be formed by chemical-mechanical polishing of a ferroelectric film. In a memory device, the capacitor is coupled to a transistor. The dielectric lining protects the ferroelectric body from etching damage during the fabrication process, obviating the need for repeated annealing to repair such damage, thereby avoiding the alteration of transistor characteristics that would be caused by such annealing.

Abstract: A method for fabricating a semiconductor device in which plural transistors including a first transistor and a second transistor are integrated includes a first step for forming the first transistor such that a distance between a drain contact and a gate electrode of the first transistor is a fist distance, and a second step for forming the second transistor such that a distance between a drain contact and a gate electrode of the second transistor is a second distance larger than the first distance.

Abstract: A ferroelectric capacitor has a top electrode, a bottom electrode, a ferroelectric body disposed between the top and bottom electrodes, and a dielectric lining disposed below the top electrode and above the bottom electrode, protecting the sides of the ferroelectric body. The ferroelectric body can be formed by chemical-mechanical polishing of a ferroelectric film. In a memory device, the capacitor is coupled to a transistor. The dielectric lining protects the ferroelectric body from etching damage during the fabrication process, obviating the need for repeated annealing to repair such damage, thereby avoiding the alteration of transistor characteristics that would be caused by such annealing.

Abstract: A ferroelectric capacitor has a top electrode, a bottom electrode, a ferroelectric body disposed between the top and bottom electrodes, and a dielectric lining disposed below the top electrode and above the bottom electrode, protecting the sides of the ferroelectric body. The ferroelectric body can be formed by chemical-mechanical polishing of a ferroelectric film. In a memory device, the capacitor is coupled to a transistor. The dielectric lining protects the ferroelectric body from etching damage during the fabrication process, obviating the need for repeated annealing to repair such damage, thereby avoiding the alteration of transistor characteristics that would be caused by such annealing.

Abstract: A memory cell array, in which a voltage that can reverse polarization is applied only to a memory cell that is an object of data writing. A semiconductor storage element is formed by a ferroelectric capacitor, a selection transistor and a control transistor. The ferroelectric capacitor is structured to be provided with a ferroelectric layer between an upper electrode and a lower electrode. The selection transistor is provided with a first main electrode, a second main electrode and a control electrode. The control transistor is provided with a first main electrode, a second main electrode and a control electrode. The lower electrode of the ferroelectric capacitor is connected with the first main electrode of the selection transistor. The second main electrode of the selection transistor is connected with the control electrode of the control transistor.

Abstract: A method in which a gate structure having a ferroelectric film and a conductor film is processed easily and without causing damage is provided. A first IrO2 film is deposited on a substrate. A ferroelectric film is formed by applying a light-sensitive sol-gel solution containing a ferroelectric material dissolved therein onto the first IrO2 film. A difference in solubility at the time of development is made between an exposed portion and an unexposed portion of the light-sensitive sol-gel solution. A second IrO2 film is deposited on the ferroelectric film. A shading film and an etching mask of predetermined patterns are formed on the second IrO2 film. The second IrO2 film is processed using the etching mask and an upper electrode is formed. The pattern of the shading film is transferred to the ferroelectric film by effecting exposure. An exposed region of the ferroelectric film is removed by effecting development. Only an unexposed region remains as a ferroelectric film.