Patents by Inventor Kouichi Yahagi
Kouichi Yahagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120320163Abstract: Two or more images having a parallax therebetween are obtained by imaging a subject from different positions using imaging units. Three-dimensional processing for three-dimensional display is applied to the two or more images, and the two or more images are displayed on a display unit. While the imaging units carry out a zoom operation, three-dimensional display with a reduced parallax between the two or more images or two-dimensional display is performed.Type: ApplicationFiled: August 30, 2012Publication date: December 20, 2012Applicant: FUJIFILM CORPORATIONInventor: Kouichi YAHAGI
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Patent number: 8294711Abstract: Two or more images having a parallax therebetween are obtained by imaging a subject from different positions using imaging units. Three-dimensional processing for three-dimensional display is applied to the two or more images, and the two or more images are displayed on a display unit. While the imaging units carry out a zoom operation, three-dimensional display with a reduced parallax between the two or more images or two-dimensional display is performed.Type: GrantFiled: September 9, 2009Date of Patent: October 23, 2012Assignee: FUJIFILM CorporationInventor: Kouichi Yahagi
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Patent number: 8199147Abstract: A subject is imaged at a predetermined time interval by a plurality of imaging units which obtains a plurality of images having a parallax of a subject viewed from different viewpoints by imaging the subject from different viewpoints. An evaluation value which includes at least one of a luminance and a high frequency component of the images obtained by the imaging units at the predetermined time interval is calculated. When the evaluation value has changed by an amount exceeding a predetermined threshold value, the distance information calculation and three-dimensional processing on the plurality of images and object are performed. Here, a relative position of the object with respect to the three-dimensional image in a three-dimensional space is changed based on the distance information such that overlapping of the object and the three-dimensional image on top of each other is prevented when the three-dimensional display is performed.Type: GrantFiled: September 25, 2009Date of Patent: June 12, 2012Assignee: FUJIFILM CorporationInventors: Eiji Ishiyama, Kouichi Yahagi, Tomonori Masuda
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Publication number: 20110193937Abstract: An image reproducing apparatus (and method) includes obtaining a plurality of original images of a subject viewed from different viewpoints for generating a three-dimensional image, generating at least one interpolation image from the plurality of original images for interpolating a viewpoint between at least the plurality of original images, generating a motion picture in which the plurality of original images and at least some of the interpolation images are arranged in the order of viewpoint, and storing the plurality of original images and the motion picture in relation to each other.Type: ApplicationFiled: October 8, 2009Publication date: August 11, 2011Inventors: Mikio Watanabe, Satoshi Nakamura, Kouichi Yahagi
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Publication number: 20110175910Abstract: Two or more images having a parallax therebetween are obtained by imaging a subject from different positions using imaging units. Three-dimensional processing for three-dimensional display is applied to the two or more images, and the two or more images are displayed on a display unit. While the imaging units carry out a zoom operation, three-dimensional display with a reduced parallax between the two or more images or two-dimensional display is performed.Type: ApplicationFiled: September 9, 2009Publication date: July 21, 2011Applicant: FUJIFILM CORPORATIONInventor: Kouichi Yahagi
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Publication number: 20110169825Abstract: A subject is imaged at a predetermined time interval by a plurality of imaging units which obtains a plurality of images having a parallax of a subject viewed from different viewpoints by imaging the subject from different viewpoints. An evaluation value which includes at least one of a luminance and a high frequency component of the images obtained by the imaging units at the predetermined time interval is calculated. When the evaluation value has changed by an amount exceeding a predetermined threshold value, the distance information calculation and three-dimensional processing on the plurality of images and object are performed. Here, a relative position of the object with respect to the three-dimensional image in a three-dimensional space is changed based on the distance information such that overlapping of the object and the three-dimensional image on top of each other is prevented when the three-dimensional display is performed.Type: ApplicationFiled: September 25, 2009Publication date: July 14, 2011Applicant: FUJIFILM CorporationInventors: Eiji Ishiyama, Kouichi Yahagi, Tomonori Masuda
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Patent number: 7286074Abstract: A semiconductor integrated circuit having a built-in A/D conversion circuit which enables, where the A/D conversion circuit is to be built into a semiconductor chip, the required capacitance of the stabilization capacitor to be connected to the output terminals of reference voltage generators for generating reference voltages to be reduced is to be provided to contribute to preventing the number of external terminals and the chip size from increasing.Type: GrantFiled: July 27, 2005Date of Patent: October 23, 2007Assignee: Renesas Technology CorporationInventors: Junya Kudoh, Kouichi Yahagi, Tatsuji Matsuura
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Patent number: 7278577Abstract: An image input system includes a solid state image pickup device and a preprocessor for performing correlated double sampling amplification on an output of the image pickup device and outputting a video signal. The preprocessor has a correlated double sampling amplifier for outputting signal information corresponding to a difference voltage between the black level in a feedthrough period of the image pickup device and a signal level in a charge signal output period; and an offset cancelling circuit for cancelling an offset voltage corresponding to the difference voltage in a state where the image pickup device is optically interrupted to the input terminal of the correlated double sampling amplifier. The correlated double sampling amplifier cancels out the offset voltage and the offset cancelling voltage as signal components of polarities opposite to each other, so that circuits following the correlated double sampling amplifier are not influenced by the offset voltage.Type: GrantFiled: April 14, 2004Date of Patent: October 9, 2007Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Kouichi Yahagi, Masumi Kasahara, Hiroki Nakajima
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Publication number: 20070007347Abstract: An image input system comprises a solid state image pickup device and a preprocessor (3) for performing correlated double sampling amplification on an output signal of the solid state image pickup device and outputting a video signal. The preprocessor comprises: a correlated double sampling amplifier (30) for outputting signal information corresponding to a difference voltage between the black level in a feedthrough period of the solid state image pickup device and a signal level in a charge signal output period; and offset cancelling means (38) for applying an offset cancelling voltage for cancelling an offset voltage corresponding to the difference voltage between the black level and the signal level in a state where the solid state image pickup device is optically interrupted to the input terminal of the correlated double sampling amplifier. The correlated double sampling amplifier cancels out the offset voltage and the offset cancelling voltage as signal components of polarities opposite to each other.Type: ApplicationFiled: May 16, 2006Publication date: January 11, 2007Inventors: Kouichi Yahagi, Masumi Kasahara, Hiroki Nakajima
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Publication number: 20060022861Abstract: A semiconductor integrated circuit having a built-in A/D conversion circuit which enables, where the A/D conversion circuit is to be built into a semiconductor chip, the required capacitance of the stabilization capacitor to be connected to the output terminals of reference voltage generators for generating reference voltages to be reduced is to be provided to contribute to preventing the number of external terminals and the chip size from increasing.Type: ApplicationFiled: July 27, 2005Publication date: February 2, 2006Inventors: Junya Kudoh, Kouichi Yahagi, Tatsuji Matsuura
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Publication number: 20040196392Abstract: An image input system comprises a solid state image pickup device and a preprocessor (3) for performing correlated double sampling amplification on an output signal of the solid state image pickup device and outputting a video signal. The preprocessor comprises: a correlated double sampling amplifier (30) for outputting signal information corresponding to a difference voltage between the black level in a feedthrough period of the solid state image pickup device and a signal level in a charge signal output period; and offset cancelling means (38) for applying an offset cancelling voltage for cancelling an offset voltage corresponding to the difference voltage between the black level and the signal level in a state where the solid state image pickup device is optically interrupted to the input terminal of the correlated double sampling amplifier. The correlated double sampling amplifier cancels out the offset voltage and the offset cancelling voltage as signal components of polarities opposite to each other.Type: ApplicationFiled: April 14, 2004Publication date: October 7, 2004Applicants: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Kouichi Yahagi, Masumi Kasahara, Hiroki Nakajima
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Patent number: 6783073Abstract: An image input system includes a solid state image pickup device and a preprocessor for performing correlated double sampling amplification on an output of the image pickup device and outputting a video signal. The preprocessor has a correlated double sampling amplifier for outputting signal information corresponding to a difference voltage between the black level in a feedthrough period of the image pickup device and a signal level in a charge signal output period; and an offset cancelling circuit for cancelling an offset voltage corresponding to the difference voltage in a state where the image pickup device is optically interrupted to the input terminal of the correlated double sampling amplifier. The correlated double sampling amplifier cancels out the offset voltage and the offset cancelling voltage as signal components of polarities opposite to each other, so that circuits following the correlated double sampling amplifier are not influenced by the offset voltage.Type: GrantFiled: July 23, 2002Date of Patent: August 31, 2004Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Kouichi Yahagi, Masumi Kasahara, Hiroki Nakajima
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Patent number: 6499663Abstract: An image input system includes a solid state image pickup device and a preprocessor for performing correlated double sampling amplification on an output of the image pickup device and outputting a video signal. The preprocessor has a correlated double sampling amplifier for outputting signal information corresponding to a difference voltage between the black level in a feedthrough period of the image pickup device and a signal level in a charge signal output period; and an offset cancelling circuit for cancelling an offset voltage corresponding to the difference voltage in a state where the image pickup device is optically interrupted to the input terminal of the correlated double sampling amplifier. The correlated double sampling amplifier cancels out the offset voltage and the offset cancelling voltage as signal components of polarities opposite to each other, so that circuits following the correlated double sampling amplifier are not influenced by the offset voltage.Type: GrantFiled: April 18, 2000Date of Patent: December 31, 2002Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.Inventors: Kouichi Yahagi, Masumi Kasahara, Hiroki Nakajima
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Publication number: 20020179712Abstract: An image input system comprises a solid state image pickup device and a preprocessor (3) for performing correlated double sampling amplification on an output signal of the solid state image pickup device and outputting a video signal. The preprocessor comprises: a correlated double sampling amplifier (30) for outputting signal information corresponding to a difference voltage between the black level in a feedthrough period of the solid state image pickup device and a signal level in a charge signal output period; and offset cancelling means (38) for applying an offset cancelling voltage for cancelling an offset voltage corresponding to the difference voltage between the black level and the signal level in a state where the solid state image pickup device is optically interrupted to the input terminal of the correlated double sampling amplifier. The correlated double sampling amplifier cancels out the offset voltage and the offset cancelling voltage as signal components of polarities opposite to each other.Type: ApplicationFiled: July 23, 2002Publication date: December 5, 2002Applicant: Hitachi, Ltd. and Hitachi Tohbu Semiconductor, Ltd.Inventors: Kouichi Yahagi, Masumi Kasahara, Hiroki Nakajima
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Analog-to-digital conversion method and apparatus with a controlled switch for high-speed conversion
Patent number: 5247301Abstract: An analog-to-digital converter receiving an analog signal and producing a digital output signal corresponding to a value of the analog signal includes a plurality of sets each having a plurality of sample-and-hold circuits having inputs connected in parallel with each other, an analog switch responsive to a control signal to apply the input analog signal to the junction of the parallel connection of the plurality of sample-and-hold circuits, and a plurality of encoders respectively connected to outputs of the plurality of sets to convert output signals of the plurality of sample-and-hold circuits into a binary signal. Each of the plurality of sample-and-hold circuits includes a series connection of a second analog switch and a capacitor and the analog-to-digital converter further includes comparators connected to outputs of the plurality of sample-and-hold circuits. Advantageously, errors in timing for sampling conducted in the plurality of sample-and-hold circuits can be eliminated.Type: GrantFiled: September 17, 1991Date of Patent: September 21, 1993Assignee: Hitachi, Ltd.Inventors: Kouichi Yahagi, Masumi Kasahara