Patents by Inventor Kouichiro Inazawa
Kouichiro Inazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7465673Abstract: A method for etching an organic anti-reflective coating (ARC) layer on a substrate in a plasma processing system comprising: introducing a process gas comprising nitrogen (N), hydrogen (H), and oxygen (O); forming a plasma from the process gas; and exposing the substrate to the plasma. The process gas can, for example, constitute an NH3/O2, N2/H2/O2, N2/H2/CO, NH3/CO, or NH3/CO/O2 based chemistry. Additionally, the process chemistry can further comprise the addition of helium. The present invention further presents a method for forming a bilayer mask for etching a thin film on a substrate, wherein the method comprises: forming the thin film on the substrate; forming an ARC layer on the thin film; forming a photoresist pattern on the ARC layer; and transferring the photoresist pattern to the ARC layer with an etch process using a process gas comprising nitrogen (N), hydrogen (H), and oxygen (O).Type: GrantFiled: December 17, 2003Date of Patent: December 16, 2008Assignee: Tokyo Electron LimitedInventors: Yoshiki Igarashi, Kouichiro Inazawa, Kimihiro Higuchi, Vaidyanathan Balasubramaniam, Eiichi Nishimura, Ralph Kim, Philip Sansone, Masaaki Hagihara
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Patent number: 7169440Abstract: A method is provided for plasma ashing to remove photoresist remnants and etch residues that are formed during preceding plasma etching of dielectric layers. The ashing method uses a two-step plasma process involving an oxygen-containing gas, where low or zero bias is applied to the substrate in the first cleaning step to remove significant amount of photoresist remnants and etch residues from the substrate, in addition to etching and removing detrimental fluoro-carbon residues from the chamber surfaces. An increased bias is applied to the substrate in the second cleaning step to remove the remains of the photoresist and etch residues from the substrate. The two-step process reduces the memory effect commonly observed in conventional one-step ashing processes. A method of endpoint detection can be used to monitor the ashing process.Type: GrantFiled: September 30, 2002Date of Patent: January 30, 2007Assignee: Tokyo Electron LimitedInventors: Vaidyanathan Balasubramaniam, Masaaki Hagiwara, Eiichi Nishimura, Kouichiro Inazawa
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Patent number: 6849559Abstract: A method is provided for plasma ashing to remove photoresist remnants and etch residues that are formed during preceding plasma etching of dielectric layers. The ashing method uses a two-step plasma process involving an hydrogen-containing gas, where low or zero bias is applied to the substrate in the first cleaning step to remove significant amount of photoresist remnants and etch residues from the substrate, in addition to etching and removing detrimental fluoro-carbon residues from the chamber surfaces. An increased bias is applied to the substrate in the second cleaning step to remove the remains of the photoresist and etch residues from the substrate. The two-step process reduces the memory effect commonly observed in conventional one-step ashing processes. A method of endpoint detection can be used to monitor the ashing process.Type: GrantFiled: September 30, 2002Date of Patent: February 1, 2005Assignee: Tokyo Electron LimitedInventors: Vaidyanathan Balasubramaniam, Yasunori Hatamura, Masaaki Hagiwara, Eiichi Nishimura, Kouichiro Inazawa
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Patent number: 6753263Abstract: A lower electrode 106 with the temperature at its mounting surface set at 40° C. is provided inside a processing chamber 104 of an etching apparatus 100. After a wafer W is placed on the lower electrode 106, a processing gas with its gas composition and gas flow rate expressed as C4F8: CH2F2: Ar=7:4:500 (sccm) is induced into the processing chamber 104 while sustaining the pressure of the atmosphere inside the processing chamber 104 at 50 (mTorr). High-frequency power at 1500 (W) with the frequency at 13.56 (MHz) is applied to the lower electrode 106 to generate plasma. With the plasma thus generated, a carbon film is formed at shoulder 207 of an SiNx film layer 206 exposed inside a contact hole 210 and, at the same time, accumulation of carbon at the bottom of the contact hole 210 is prevented, to form a contact hole 210 achieving a high aspect ratio while preventing damage to the SiNx film layer.Type: GrantFiled: February 5, 2001Date of Patent: June 22, 2004Assignee: Tokyo Electron LimitedInventors: Youbun Ito, Masahiro Yamada, Kouichiro Inazawa
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Patent number: 6737350Abstract: A semiconductor device using, e.g., a fluorine containing carbon film, as an interlayer dielectric film is produced by a dual damascene method which is a simple technique. After an dielectric film, e.g., an SiO2 film 3, is deposited on a substrate 2, the SiO2 film 3 is etched to form a via hole 31 therein, and then, a top dielectric film, e.g., a CF film 4, is deposited on the top face of the SiO2 film 3. If the CF film is deposited by activating a thin-film deposition material having a bad embedded material, e.g., C6F6 gas, as a plasma, the CF film 4 can be deposited on the top face of the SiO2 film 3 while inhibiting the CF film from being embedded into the via hole 31. Subsequently, by etching the CF film 4 to form a groove 41 therein, it is possible to easily produce a dual damascene shape wherein the groove 41 is integrated with the via hole 31.Type: GrantFiled: September 21, 2000Date of Patent: May 18, 2004Assignee: Tokyo Electron LimitedInventors: Takashi Akahori, Kouichiro Inazawa, Kouji Senoo, Masaaki Hagiwara
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Patent number: 6642149Abstract: In a processing chamber of an etching apparatus a lower electrode and an upper electrode grounded through a processing container are disposed oppositely to each other. A first high frequency power supply section composed of a first filter, a first matching device, and a first power source, and a second high frequency power supply section composed of a second filter, a second matching device, and a second power source are connected to the lower electrode. A superimposed power of two frequencies composed of a first high frequency power component of at least 10 MHz produced from the first power source and a second high frequency power component of at least 2 MHz produced from the second power source is applied to the lower electrode. Ions in the plasma do not accelerated by changes of electric field in the processing chamber, but are accelerated by a self-bias voltage and collide only against a wafer on the lower electrode.Type: GrantFiled: November 4, 2002Date of Patent: November 4, 2003Assignees: Tokyo Electron Limited, Kabushiki Kaisha ToshibaInventors: Tomoki Suemasa, Tsuyoshi Ono, Kouichiro Inazawa, Makoto Sekine, Itsuko Sakai, Yukimasa Yoshida
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Publication number: 20030194876Abstract: A method is provided for plasma ashing to remove photoresist remnants and etch residues that are formed during preceding plasma etching of dielectric layers. The ashing method uses a two-step plasma process involving an hydrogen-containing gas, where low or zero bias is applied to the substrate in the first cleaning step to remove significant amount of photoresist remnants and etch residues from the substrate, in addition to etching and removing detrimental fluoro-carbon residues from the chamber surfaces. An increased bias is applied to the substrate in the second cleaning step to remove the remains of the photoresist and etch residues from the substrate. The two-step process reduces the memory effect commonly observed in conventional one-step ashing processes. A method of endpoint detection can be used to monitor the ashing process.Type: ApplicationFiled: September 30, 2002Publication date: October 16, 2003Applicant: TOKYO ELECTRON LIMITEDInventors: Vaidyanathan Balasubramaniam, Yasunori Hatamura, Masaaki Hagiwara, Eiichi Nishimura, Kouichiro Inazawa
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Publication number: 20030192856Abstract: A method is provided for plasma ashing to remove photoresist remnants and etch residues that are formed during preceding plasma etching of dielectric layers. The ashing method uses a two-step plasma process involving an oxygen-containing gas, where low or zero bias is applied to the substrate in the first cleaning step to remove significant amount of photoresist remnants and etch residues from the substrate, in addition to etching and removing detrimental fluorocarbon residues from the chamber surfaces. An increased bias is applied to the substrate in the second cleaning step to remove the remains of the photoresist and etch residues from the substrate. The two-step process reduces the memory effect commonly observed in conventional one-step ashing processes. A method of endpoint detection can be used to monitor the ashing process.Type: ApplicationFiled: September 30, 2002Publication date: October 16, 2003Applicant: TOKYO ELECTRON LIMITEDInventors: Vaidyanathan Balasubramaniam, Masaaki Hagiwara, Eiichi Nishimura, Kouichiro Inazawa
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Patent number: 6602435Abstract: A processing gas constituted of C5F8, O2 and Ar achieving a flow rate ratio of 1≦C5F8 flow rate/O2 flow rate≦1.625 is supplied into a processing chamber 102 of an etching apparatus 100 and the atmosphere pressure is set within a range of 45 mTorr˜50 mTorr. High-frequency power is applied to a lower electrode 110 sustained within a temperature range of 20° C.˜40° C. on which a wafer W is mounted to raise the processing gas to plasma, and using the plasma, a contact hole 210 is formed at an SiO2 film 208 on an SiNx film 206 formed at the wafer W. The use of C5F8 and O2 makes it possible to form a contact hole 210 achieving near-perfect verticality at the SiO2 film 208 and also improves the selection ratio of the SiO2 film 208 relative to the SiNx film 206. C5F8, which becomes decomposed over a short period of time when released into the atmosphere, does not induce the greenhouse effect.Type: GrantFiled: June 26, 2000Date of Patent: August 5, 2003Assignee: Tokyo Electron LimitedInventors: Masahiro Yamada, Youbun Ito, Kouichiro Inazawa
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Publication number: 20030054647Abstract: In a processing chamber of an etching apparatus a lower electrode and an upper electrode grounded through a processing container are disposed oppositely to each other. A first high frequency power supply section composed of a first filter, a first matching device, and a first power source, and a second high frequency power supply section composed of a second filter, a second matching device, and a second power source are connected to the lower electrode. A superimposed power of two frequencies composed of a first high frequency power component of at least 10 MHz produced from the first power source and a second high frequency power component of at least 2 MHz produced from the second power source is applied to the lower electrode. Ions in the plasma do not accelerated by changes of electric field in the processing chamber, but are accelerated by a self-bias voltage and collide only against a wafer on the lower electrode.Type: ApplicationFiled: November 4, 2002Publication date: March 20, 2003Inventors: Tomoki Suemasa, Tsuyoshi Ono, Kouichiro Inazawa, Makoto Sekine, Itsuko Sakai, Yukimasa Yoshida
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Patent number: 6488863Abstract: An etching gas is supplied into a process chamber and turned into plasma so as to etch a silicon nitride film arranged on a field silicon oxide film on a wafer (w). A mixture gas containing at least CH2F2 gas and O2 gas is used as the etching gas. Parameters for planar uniformity, by which the etching apparatus is set in light of a set value of the planar uniformity, include the process pressure and the mixture ratio (CH2F2/O2) of the mixture gas. As the set value of the planar uniformity is more strict, either one of the process pressure and the mixture ratio is set higher.Type: GrantFiled: October 5, 2001Date of Patent: December 3, 2002Assignee: Tokyo Electron LimitedInventors: Koichi Yatsuda, Tetsuya Nishiara, Kouichiro Inazawa, Shin Okamoto
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Patent number: 6465359Abstract: A method and system for processing a substrate in the presence of high purity C5F8. When processing oxides and dielectrics in a gas plasma processing system, C5F8 is used in combination with a carrier gas (e.g., Ar) and one or more of CO and O2. When using a silicon nitride (SixNy) layer as an etch stop, effective etching is performed due to the selectivity of oxides versus silicon nitride. The method is used when etching down to self-aligning contacts and other layers. The method may be practiced with or without using an anti-reflective coating underneath the photoresist layer.Type: GrantFiled: September 17, 1999Date of Patent: October 15, 2002Assignee: Tokyo Electron Ltd.Inventors: Masahiro Yamada, Youbun Ito, Kouichiro Inazawa, Abron Toure, Kunihiko Hinata, Hiromi Sakima
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Publication number: 20020084254Abstract: An etching gas is supplied into a process chamber and turned into plasma so as to etch a silicon nitride film arranged on a field silicon oxide film on a wafer (w). A mixture gas containing at least CH2F2 gas and O2 gas is used as the etching gas. Parameters for planar uniformity, by which the etching apparatus is set in light of a set value of the planar uniformity, include the process pressure and the mixture ratio (CH2F2/O2) of the mixture gas. As the set value of the planar uniformity is more strict, either one of the process pressure and the mixture ratio is set higher.Type: ApplicationFiled: October 5, 2001Publication date: July 4, 2002Applicant: Tokyo Electron LimitedInventors: Koichi Yatsuda, Tetsuya Nishiara, Kouichiro Inazawa, Shin Okamoto
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Publication number: 20020030174Abstract: A method and system for processing a substrate in the presence of high purity C5F8. When processing oxides and dielectrics in a gas plasma processing system, C5F8 is used in combination with a carrier gas (e.g., Ar) and one or more of CO and O2. When using a silicon nitride (SixNy) layer as an etch stop, effective etching is performed due to the selectivity of oxides versus silicon nitride. The method is used when etching down to self-aligning contacts and other layers. The method may be practiced with or without using an anti-reflective coating underneath the photoresist layer.Type: ApplicationFiled: September 17, 1999Publication date: March 14, 2002Inventors: MASAHIRO YAMADA, YOUBUN ITO, KOUICHIRO INAZAWA, ABRON TOURE, KUNIHIKO HINATA, HIROMI SAKIMA
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Patent number: 6159862Abstract: A method and system for processing a substrate in the presence of high purity C.sub.5 F.sub.8. When processing oxides and dielectrics in a gas plasma processing system, C.sub.5 F.sub.8 is used in combination with a carrier gas (e.g., Ar) and one or more of CO and O.sub.2. When using a silicon nitride (Si.sub.x N.sub.y) layer as an etch stop, effective etching is performed due to the selectivity of oxides versus silicon nitride. The method is used when etching down to self-aligning contacts and other layers. The method may be practiced with or without using an anti-reflective coating underneath the photoresist layer.Type: GrantFiled: June 1, 1998Date of Patent: December 12, 2000Assignee: Tokyo Electron Ltd.Inventors: Masahiro Yamada, Youbun Ito, Kouichiro Inazawa, Abron Toure, Kunihiko Hinata, Hiromi Sakima
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Patent number: 6089181Abstract: In a plasma etching apparatus, a process gas is supplied into a process chamber and converted into plasma by means of RF discharge, and a semiconductor wafer placed on a lower electrode is etched by the plasma. An RF power supply mechanism is connected to the lower electrode for applying thereto a superposed RF power for forming an RF electric field in the process chamber. The RF power supply mechanism has first and second RF power supplies for respectively oscillating a low frequency RF component and a high frequency RF component having a higher frequency than the low frequency RF component. The high frequency RF component from the second frequency RF component supply has its wave form modulated by a modulator on the basis of the wave form of the low frequency RF component from the first frequency RF power supply. Thereafter, the modulated high frequency RF component and the low frequency RF component are superposed upon each other.Type: GrantFiled: July 21, 1997Date of Patent: July 18, 2000Assignee: Tokyo Electron LimitedInventors: Tomoki Suemasa, Tsuyoshi Ono, Kouichiro Inazawa
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Patent number: 5721090Abstract: An etching method comprising the steps of forming an etched layer on a wafer and covering the etched layer with an anti-reflection cover and then the anti-reflection cover with a photoresist film, pattern-exposing the photoresist film, developing the exposed photoresist film to form pattern openings in each of which the anti-reflection cover is exposed, and carrying the wafer into a chamber, exhausting the chamber to decompressed atmosphere, and introducing a mixed gas of C.sub.4 F.sub.8 gas and at least one of O.sub.2 and N.sub.2 gases into the process chamber to generate plasma of this mixed gas and act active species in this plasma on the wafer, whereby the anti-reflection cover which is exposed in each of the pattern openings is etched and the etched layer is then etched without etching the photoresist film formed on an inner surface each pattern opening.Type: GrantFiled: September 20, 1995Date of Patent: February 24, 1998Assignee: Tokyo Electron LimitedInventors: Shin Okamoto, Kouichiro Inazawa, Sachiko Furuya, Maki Koizumi