Patents by Inventor Kouichiro Okumura

Kouichiro Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5541546
    Abstract: A signal level conversion circuit is constructed with an inverter (103, 104) provided between a voltage source terminal (V2) and ground, first and second enhancement NMOS transistors (101, 107) connected in parallel to each other and provided between a signal input terminal (I) and an input node of an inverter. An enhancement PMOS transistor (102) is provided between the input node of the inverter and the voltage source terminal (V2). Gate electrodes of the first NMOS and the PMOS transistors are connected to an output of the inverter and a gate electrode of the second NMOS transistor (107) is connected to a constant voltage source (V1) of which voltage level is greater than a threshold voltage of the second NMOS transistor (107) and smaller than a sum of an input signal voltage inputted to the input terminal and the threshold voltage of the second NMOS transistor.
    Type: Grant
    Filed: February 21, 1995
    Date of Patent: July 30, 1996
    Assignee: NEC Corporation
    Inventor: Kouichiro Okumura