Patents by Inventor Kouichirou Yamaguchi

Kouichirou Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor storage device
    Patent number: 9613720
    Abstract: A semiconductor storage device has a memory cell array, a plurality of word lines, a plurality of bit lines, and a plurality of blocks including a group of at least some memory cells, a defect information storage block that stores defect information in the memory cell array, a first defect detection circuitry that reads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is a defect in the defect information storage block, a second defect detection circuitry that changes a read voltage level for reading the data of the memory cells, rereads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is the defect in the defect information storage block, and a defect determination circuitry that determines the defect information storage block as a defective block.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: April 4, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kouichirou Yamaguchi, Makoto Miakashi, Hitoshi Shiga, Noboru Shibata
  • SEMICONDUCTOR STORAGE DEVICE
    Publication number: 20160189801
    Abstract: A semiconductor storage device has a memory cell array, a plurality of word lines, a plurality of bit lines, and a plurality of blocks including a group of at least some memory cells, a defect information storage block that stores defect information in the memory cell array, a first defect detection circuitry that reads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is a defect in the defect information storage block, a second defect detection circuitry that changes a read voltage level for reading the data of the memory cells, rereads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is the defect in the defect information storage block, and a defect determination circuitry that determines the defect information storage block as a defective block.
    Type: Application
    Filed: March 3, 2016
    Publication date: June 30, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kouichirou YAMAGUCHI, Makoto Miakashi, Hitoshi Shiga, Noboru Shibata
  • Combination re-conditioning unit and illuminating appliance for use with central air conditioning system
    Patent number: 4076073
    Abstract: A central air conditioning system for a multistory, multiroom building is arranged with a local re-conditioning unit mounted within a ceiling chamber of the building and combined with an illuminating appliance. Air in the space to be air conditioned is admitted to the re-conditioning unit through an air inlet opening formed in the illuminating appliance and is withdrawn from the re-conditioning unit into the space to be air conditioned through an air outlet opening also formed in the illuminating appliance.
    Type: Grant
    Filed: January 26, 1976
    Date of Patent: February 28, 1978
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshio Yamamoto, Jyoji Kamata, Shigeo Murase, Kouichirou Yamaguchi