Abstract: A device is provided for static random access memories (SRAM's), including an apparatus capable of executing more than one kind of logical operation for each memory cell, with a relatively small number of elements, and the same configuration for different types of operations. These operations include (1) the normal read-out/write-in operations; (2) inverting the contents of one sequence of memory cells and storing either the result or the result shifted one bit to the right in a second sequence of memory cells; (3) storing the result of an OR operation between two sequences of memory cells in a third sequence of memory cells; and (4) initializing each memory cell. The left or right node potential of each memory cell may also be individually accessed. Each operation between memory cells is simultaneous with the direct writing of the result into other memory cells, so no temporary holding cells are required and the operation is accomplished at high speed.