Patents by Inventor Kouji Araki

Kouji Araki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7391386
    Abstract: An array antenna apparatus (100) includes a radiating element (A0) for receiving a transmitted radio signal, two parasitic elements (A1, A2), and two variable reactance elements (12-1, 12-2) connected to the respective parasitic elements (A1, A2), and a directivity characteristic of the array antenna apparatus is changed by changing reactances set to the variable reactance elements. An antenna controller (10) selects and sets one reactance to be set from those in a first case in which a first reactance set is set to the two variable reactance elements (12-1, 12-2) and a second case in which a second reactance set is set to the two variable reactance elements (12-1, 12-2) to be able to obtain a diversity gain equal to or larger than a predetermined value, based on a received radio signal, based on signal quality of the radio signal.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: June 24, 2008
    Assignee: Advanced Telecommunications Research Institute International
    Inventors: Takuma Sawaya, Kyoichi Iigusa, Makoto Taromaru, Takashi Ohira, Kouji Araki
  • Patent number: 7263766
    Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: September 4, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Ishiwata, Kosoku Nagata, Toshio Shimizu, Hiroyuki Hiramoto, Yasuhiko Taniguchi, Kouji Araki, Hiroshi Fukuyoshi, Hiroshi Komorita
  • Publication number: 20030168729
    Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.
    Type: Application
    Filed: January 27, 2003
    Publication date: September 11, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yutaka Ishiwata, Kosoku Nagata, Toshio Shimizu, Hiroyuki Hiramoto, Yasuhiko Taniguchi, Kouji Araki, Hiroshi Fukuyoshi, Hiroshi Komorita
  • Patent number: 6605868
    Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: August 12, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Ishiwata, Kosoku Nagata, Toshio Shimizu, Hiroyuki Hiramoto, Yasuhiko Taniguchi, Kouji Araki, Hiroshi Fukuyoshi, Hiroshi Komorita
  • Publication number: 20020066953
    Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.
    Type: Application
    Filed: December 9, 1999
    Publication date: June 6, 2002
    Inventors: YUTAKA ISHIWATA, KOSOKU NAGATA, TOSHIO SHIMIZU, HIROYUKI HIRAMOTO, YASUHIKO TANIGUCHI, KOUJI ARAKI, HIROSHI FUKUYOSHI, HIROSHI KOMORITA
  • Patent number: 5338392
    Abstract: In a method for manufacturing a laminated plate used in a semiconductor device according to the present invention, a conductive member is processed to form a frame and a wiring pattern supported by the frame integrally with each other, the wiring pattern is bonded to the major surface of a base member by high-temperature heating, using the frame as a guide, thereby to form a laminated layer, and the frame is removed from the laminated layer to form a desirable laminated plate.
    Type: Grant
    Filed: October 7, 1993
    Date of Patent: August 16, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kouji Araki
  • Patent number: 5332921
    Abstract: A resin-seal type semiconductor device includes a main substrate divided into first and second surfaces on which first and second insulating substrates are respectively provided. Circuit wiring patterns and first end portions of outer leads are provided on the first and second insulating substrates. Semiconductor elements are soldered onto the wiring patterns and coated with a surface protection material. The main substrate is then folded over so that the first and second surfaces oppose one another and the device acquires a U-shaped cross-section. A space formed between the first and second surfaces inside the U-shape is sealed with a resin such that second end portions of the outer leads are exposed from the resin.
    Type: Grant
    Filed: April 27, 1993
    Date of Patent: July 26, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noriaki Dousen, Nobuyuki Sato, Kouji Araki
  • Patent number: 5295044
    Abstract: A plurality of circuit boards are used and frames are attached to the circuit boards to surround the peripheral portions thereof. Since connection terminals electrically connected to the respective circuit boards are attached to the respective frames, a semiconductor device having semiconductor elements mounted at high density can be formed by stacking the first and second frames on each other and setting the respective connection terminals in contact with each other to electrically connect the circuit boards to each other.
    Type: Grant
    Filed: September 25, 1992
    Date of Patent: March 15, 1994
    Assignee: Kabushiki Kaisah Toshiba
    Inventors: Kouji Araki, Shinjiro Kojima, Wataru Takahashi
  • Patent number: 5113241
    Abstract: A semiconductor device comprises a plurality of pellets fixed on a bed by a conductive adhesive agent, an insulating substrate having a junction wiring fixed on the bed between the semiconductor pellets, and wires for connecting the pellets and insulating substrate. The insulating substrate is fixed on the bed by an insulating adhesive agent including filling material such as particles of silicon dioxide and metal particles. The surfaces of the filling material particles are coated with an oxide film.
    Type: Grant
    Filed: December 14, 1990
    Date of Patent: May 12, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoru Yanagida, Kouji Araki, Hikaru Okunoyama, Tetsunori Niimi
  • Patent number: 4911350
    Abstract: A wire bonding capillary for a bonding process comprises an elongated capillary body having an axial bore through the body for receiving a wire of a predetermined diameter to be bonded, and a working face on one end of the body for applying force to the bonding wire during the bonding process. The working face includes a first surface portion surrounding the bore and having a first radius of curvature, and a second surface portion adjacent to the first surface portion and having a second radius of curvature smaller than the first radius curvature.
    Type: Grant
    Filed: March 24, 1989
    Date of Patent: March 27, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouji Araki, Toshihiro Kato