Patents by Inventor Kouji Hayano
Kouji Hayano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6434661Abstract: A semiconductor memory device is provided with a static random access memory (SRAM) serving as a cache memory and a dynamic random access memory (DRAM) serving as a main memory. A bi-directional data transfer circuit is arranged for transfer of data blocks between the SRAM and the DRAM. A command register is provided for holding command data to set operation modes such as a data output mode of the memory device. The data output mode may include a transparent mode, a latched mode and a registered mode selected depending on a data combination at data input terminals of the memory device. An output circuit for providing a selected data output mode includes an output latch circuit for latching data on read data buses in response to clock signals, and an output buffer for outputting data from the output latches to a data output terminal.Type: GrantFiled: August 17, 2000Date of Patent: August 13, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuhiro Konishi, Katsumi Dosaka, Kouji Hayano, Masaki Kumanoya, Akira Yamazaki, Hisashi Iwamoto
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Patent number: 6356484Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: January 10, 2000Date of Patent: March 12, 2002Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Yasuhiro Konishi, Katsumitsu Himukashi, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Ishizuka, Tsukasa Saika
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Patent number: 6333873Abstract: A semiconductor memory device receives an external control signal repeatedly generated independently of an access to the memory device. The memory device includes an internal voltage generator for generating a desired internal voltage in response to the control signal. The internal voltage generator includes a charge pump circuit responsive to the control signal. The internal voltage may provide a negative voltage such as a substrate bias voltage, or may be a positive voltage boosted over an operating power supply voltage and used as a boosted word line drive signal. This scheme eliminates an oscillator for generating a repeated clock signal to the charge pump circuit, leading to reduced current consumption and reduced chip area for the semiconductor memory device.Type: GrantFiled: September 29, 1997Date of Patent: December 25, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masaki Kumanoya, Katsumi Dosaka, Yasuhiro Konishi, Akira Yamazaki, Hisashi Iwamoto, Kouji Hayano
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Publication number: 20010040827Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRUM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: ApplicationFiled: January 10, 2000Publication date: November 15, 2001Inventors: KATSUMI DOSAKA, MASAKI KUMANOYA, YASUHIRO KONISHI, KATSUMITSU HIMUKASHI, KOUJI HAYANO, AKIRA YAMAZAKI, HISASHI IWAMOTO, HIDEAKI ABE, YASUHIRO ISHIZUKA, TSUKASA SAIKI
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Patent number: 6170036Abstract: A semiconductor memory device is configured to include a static random access memory (SRAM) array and a dynamic random access memory (DRAM) array. The memory device includes an internal data line which enables the transfer of data blocks between the SRAM and DRAM arrays. Data transfer circuitry is provided separately from the internal data line and includes a latch circuit for latching the data to be transferred. The data transfer circuitry is responsive to a transfer designating signal.Type: GrantFiled: December 23, 1996Date of Patent: January 2, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuhiro Konishi, Katsumi Dosaka, Kouji Hayano, Masaki Kumanoya, Akira Yamazaki, Hisashi Iwamoto
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Patent number: 6026029Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: May 29, 1997Date of Patent: February 15, 2000Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5848004Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: March 28, 1996Date of Patent: December 8, 1998Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5652723Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: April 15, 1992Date of Patent: July 29, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5650968Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: May 21, 1996Date of Patent: July 22, 1997Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5629895Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: April 30, 1996Date of Patent: May 13, 1997Assignees: Mitsubishi Electric Engineering Co., Ltd., Mitsubishi Denki Kabushiki KaishaInventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5623454Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: February 9, 1996Date of Patent: April 22, 1997Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5603009Abstract: A semiconductor memory device containing a cache includes a static random access memory (SRAM) as a cache memory, and a dynamic random access memory (DRAM) as a main memory. Collective transfer of data blocks is possible between the DRAM and the SRAM through a bi-directional data transfer gate circuit and through an internal data line. A DRAM row decoder and a DRAM column decoder are provided in the DRAM. A SRAM row decoder and an SRAM column decoder are provided in the SRAM. Addresses of the SRAM and DRAM can be independently applied. The data transfer gate includes a latch circuit for latching data from the SRAM, which serves as a high speed memory, an amplifier circuit and a gate circuit for amplifying data from the DRAM, which serves as a large capacity memory, and for transmitting the amplified data to the SRAM, and a gate circuit, responsive to a DRAM write enable signal for transmitting write data to corresponding memory cells of the DRAM.Type: GrantFiled: December 14, 1994Date of Patent: February 11, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuhiro Konishi, Katsumi Dosaka, Kouji Hayano, Masaki Kumanoya, Akira Yamazaki, Hisashi Iwamoto
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Patent number: 5583813Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: June 5, 1995Date of Patent: December 10, 1996Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5559750Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: June 5, 1995Date of Patent: September 24, 1996Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5544121Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: June 5, 1995Date of Patent: August 6, 1996Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5408139Abstract: A semiconductor integrated circuit device includes an internal circuit and a power-on reset signal generation circuit. The internal circuit includes an output node and an input for a power-on reset signal. The potential of the output node becomes indefinite immediately after the power-up. The internal circuit also has a function of forcing the potential of the output node to a high level in response to the power-on reset signal being applied for a sufficiently long period of time. The power-on reset signal generation circuit has a reset input, an input connected to the output node, and an output connected to the input for the power-on reset signal in the internal circuit. The power-on reset signal generation circuit starts generating the power-on reset signal in response to input of a reset signal, and stops the generation of the power-on reset signal in response to the potential of the output node attaining the high level.Type: GrantFiled: November 5, 1993Date of Patent: April 18, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Kouji Hayano