Patents by Inventor Kouji Ishikura

Kouji Ishikura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100025737
    Abstract: A field-effect transistor according to the present invention includes a source electrode that is formed in an active region, and a drain electrode that is formed in the active region. Further, the field-effect transistor includes a gate electrode that is formed in the active region and disposed between the source electrode and the drain electrode, a field plate electrode that is formed in a vicinity of the gate electrode outside a region disposed between the gate electrode and the source electrode, and an FP pad that is included in the FP electrode, the FP pad being formed outside the active region and being grounded.
    Type: Application
    Filed: July 28, 2009
    Publication date: February 4, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Kouji Ishikura
  • Publication number: 20040164374
    Abstract: A field effect transistor includes: a source electrode and a drain electrode formed above a semiconductor active layer; an insulating film formed between the source electrode and the drain electrode above the semiconductor active layer so as to have an opening in which its side wall on a drain electrode side includes a tapered portion formed so as to be inclined from a plane perpendicular to an upper surface of the semiconductor active layer toward the drain electrode; and a gate electrode contacted to the semiconductor active layer through the opening so as to cover at least the side wall on the drain electrode side. Thus, there is provided the field effect transistor which has high breakdown voltage and high linear gain characteristics.
    Type: Application
    Filed: February 17, 2004
    Publication date: August 26, 2004
    Applicant: NEC COMPOUND SEMICONDUCTOR DEVICES, LTD.
    Inventor: Kouji Ishikura
  • Patent number: 6316827
    Abstract: A semiconductor device of the present invention includes ohmic source plate electrodes, gate plate electrodes, and drain plate electrodes in parallel from each other in a heat generating region various designs are used to more evenly distribute heat generated in the semiconductor device. A first example has gold-plate electrodes formed on the respective source and drain plate electrodes in parallel with the ohmic plate electrodes. The gold-plate electrode arranged at the central portion of the heat generating region plate electrodes has the widest width and gold-plate electrodes arranged toward the center portion to the peripheral portion of the heat generating region narrow gradually. By the structure mentioned above, the semiconductor device of the present invention has uniform temperature distribution in a heat generating region. A second example uses a plurality of stripe plates perpendicular to the ohmic plate electrodes.
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: November 13, 2001
    Assignee: NEC Corporation
    Inventors: Kazunori Asano, Kouji Ishikura
  • Patent number: 6046481
    Abstract: A semiconductor device includes a bias circuit for applying a bias to a transistor in which the semiconductor comprises a two-terminal element, connected between an external power source and at least an input of the transistor, having a first conductive contact layer connected to the input of the transistor, a second conductive contact layer connected to the external power source, and a semiconductor layer having a semi-insulation intervened between the first and second conductive contact layers, thereby reducing the thermal runaway caused by temperature rise.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: April 4, 2000
    Assignee: NEC Corporation
    Inventors: Kouji Ishikura, Mikio Kanamori