Abstract: A microprocessor incorporating a cache memory unit according to the present invention sets at the register the number of bus cycles activated by the bus cycle control circuit for replacement when a miss occurs at the cache memory, through the program executed at the instruction execution unit according to whether the accessed data are contiguous or non-contiguous. The number counted at the counter of the activated bus cycles and the number set and held at the register are compared by the comparer. The comparer outputs the replacement completion signal when they are identical. The cache control circuit outputs the replacement request signal to request bus cycle activation to the bus cycle control circuit until receipt of the replacement completion signal from the comparer.

Abstract: A microcomputer development support system for a microprocessor, includes an instruction substituting circuit tracing a memory access performed by the microprocessor and substituting a predetermined branch instruction for an instruction which is read out from a predetermined address of a user memory by the microprocessor, and a background monitor configured to give the microprocessor a memory space which is separated from the user memory but is peculiar to the microcomputer development support system. After the predetermined branch instruction has been substituted and after a break acknowledge signal informing an execution of the predetermined branch instruction has been activated, the microcomputer development support system executes a program stored in the background monitor. At the same time, the microcomputer puts the cache memory into the "cache off" condition when it starts to execute the program of the background monitor.

Abstract: A cache memory unit to be incorporated in a microprocessor reduces overhead caused by cache misses by processing all main memory replacement data at the same time as their registration or storage in the cache memory during a replacement access cycle. For this purpose, the cache memory unit includes a prefetch pointer to store the address for retrieval of cache memory, an address updater to update an internal address of the cache memory, and a cache control circuit to control the cache memory unit. When a cache miss occurs, the address causing the miss is stored in a replacement address register and, until the main memory replacement data is stored in the cache memory, the contents in the replacement address register are output to an internal address bus. On the other hand, the contents in the prefetch pointer are selectively updated.

Abstract: A debugger for a microprocessor, includes an instruction substituting circuit for tracing a memory access performed by the microprocessor and for substituting a predetermined branch instruction for an instruction which is read out from a predetermined address by the microprocessor; A background monitor is configured to give the microprocessor a memory space which is separated from the user space and is unique to the debugger. After the predetermined branch instruction has been substituted and after a break acknowledge signal indicating that an execution of the predetermined branch instruction has been activated, the debugger executes a program stored in the background monitor, and supplies a cache clear signal to the cache clear terminal at the start and end of the program in the background monitor.

Abstract: A data processor includes a first circuit for decoding a sequence of instruction including a conditional branch instruction in such a manner that said conditional branch instruction is decoded and an instruction fetched after said conditional branch instruction is decoded before a branch condition for said conditional branch instruction has not decided. Said first circuit generates an operand address for the decoded instruction and a first signal indicating that said operand address is one generated before a branch condition is decided. A second circuit generates, after decision of said branch condition, a second signal indicating whether or not an instruction decoded after said conditional branch instruction is executed. The bus interface circuit performs replacement of a content of an associative memory. A control circuit receives the first and second signals and operates to hold replacement of a content of the associative memory.

Abstract: A microprogram controller advances the initiation of a string of microinstructions for certain macroinstructions to enhance the overall speed of instruction execution. The microprogram controller includes a memory (50) for storing microinstructions and a generator (30) for generating an initial microinstruction of a certain macroinstruction. A selector (60) selects one of a microinstruction read out of the memory and the initial microinstruction from the generator and latches the selected microinstruction in a microinstruction register (70). The initial microinstruction from the generator is first latched into the register and executed while a succeeding microinstruction is read out of the memory.