Abstract: Solid-state imaging elements that prevent deterioration of image quality, and reduce power consumption and AD-conversion time are disclosed. In one example, a solid-state imaging element includes a first comparator that uses a first voltage corresponding to an input voltage received from a first pixel, in reference to a first voltage difference between the input voltage and a first reference voltage, and that outputs a comparison result between the input voltage and the first reference voltage in reference to a second voltage difference, and a second comparator that outputs a comparison result of comparison between the input voltage and the second reference voltage in reference to a fourth voltage difference.

Abstract: A degree of freedom in design is improved in a solid-state imaging element in which a logic gate is provided in a comparator. A comparison circuit compares an input potential which has been input with a predetermined reference potential and outputs any one of a pair of output potentials as a comparison result. A level shift circuit outputs any one of a pair of shift potentials having a larger potential difference than the pair of output potentials as an output signal on the basis of the comparison result. The logic gate determines whether or not the output signal is higher than a predetermined threshold between the pair of shift potentials and outputs a determination result. A counter counts a count value over a period until the determination result is inverted.

Abstract: The present disclosure provides an imaging device capable of suppressing, when an analog pixel signal is compared with a predetermined reference signal, an error in inversion timing of the comparison result. The imaging device according to the present disclosure includes: a load current source; a comparator that is provided between a signal line for transmitting an analog pixel signal read from a pixel and the load current source and compares the analog pixel signal with a predetermined reference signal; and a negative capacitance circuit connected to the signal line. The load current source has two cascode-connected transistors. The negative capacitance circuit applies a voltage of the signal line to a common connection node of the two transistors of the load current source via a capacitive element without logic inversion.

Abstract: An imaging element of the present disclosure includes an analog-to-digital converter configured to convert multiple analog pixel signals that are acquired under multiple imaging conditions different from each other and that are output from a pixel, to multiple digital pixel signals, a threshold setting unit configured to set, on an input side of the analog-to-digital converter, a threshold that is randomly varied, a comparison unit configured to use, as a comparison threshold, the threshold set by the threshold setting unit and compare the comparison threshold with one of the multiple analog pixel signals, and a selection unit configured to select and output, on the basis of a result of comparison from the comparison unit, one of the multiple digital pixel signals that are output from the analog-to-digital converter.

Abstract: An imaging element of the present disclosure includes an analog-to-digital converter configured to convert multiple analog pixel signals that are acquired under multiple imaging conditions different from each other and that are output from a pixel, to multiple digital pixel signals, a threshold setting unit configured to set, on an input side of the analog-to-digital converter, a threshold that is randomly varied, a comparison unit configured to use, as a comparison threshold, the threshold set by the threshold setting unit and compare the comparison threshold with one of the multiple analog pixel signals, and a selection unit configured to select and output, on the basis of a result of comparison from the comparison unit, one of the multiple digital pixel signals that are output from the analog-to-digital converter.

Abstract: Solid-state imaging elements that prevent deterioration of image quality, and reduce power consumption and AD-conversion time are disclosed. In one example, a solid-state imaging element includes a first comparator that uses a first voltage corresponding to an input voltage received from a first pixel, in reference to a first voltage difference between the input voltage and a first reference voltage, and that outputs a comparison result between the input voltage and the first reference voltage in reference to a second voltage difference, and a second comparator that outputs a comparison result of comparison between the input voltage and the second reference voltage in reference to a fourth voltage difference.

Abstract: The present invention relates to a solid-state image sensor including a pixel array section including a plurality of unit pixels each having a photoelectric conversion unit, the plurality of unit pixels being arranged in a matrix, a sample-and-hold unit configured to sample and hold a pixel signal output from the unit pixel through a vertical signal line provided in association with column arrangement of the pixel array section, and an analog-to-digital conversion unit configured to convert a pixel signal output from the sample-and-hold unit into a digital signal. Then, the sample-and-hold unit has two sample-and-hold circuits in parallel for one vertical signal line, and at least one of the two sample-and-hold circuits has at least two sampling capacitors.

Abstract: In a solid-state imaging element in which an ADC is disposed, deterioration of conversion accuracy of the ADC caused by a dark current is inhibited. A signal voltage sample-and-hold circuit samples and holds, as a sample signal voltage, a voltage obtained by dividing a difference between a voltage of a vertical signal line corresponding to a light reception amount in a pixel and a predetermined variable reference voltage. An analog-to-digital converter converts an analog signal corresponding to the sample signal voltage to a digital signal. A reference voltage control section performs control to modulate a value of the variable reference voltage according to a dark current amount in the pixel.

Abstract: In a solid-state imaging element in which an ADC is disposed, deterioration of conversion accuracy of the ADC caused by a dark current is inhibited. A signal voltage sample-and-hold circuit samples and holds, as a sample signal voltage, a voltage obtained by dividing a difference between a voltage of a vertical signal line corresponding to a light reception amount in a pixel and a predetermined variable reference voltage. An analog-to-digital converter converts an analog signal corresponding to the sample signal voltage to a digital signal. A reference voltage control section performs control to modulate a value of the variable reference voltage according to a dark current amount in the pixel.

Abstract: A vehicular display device according to an embodiment includes a light shielding housing fixed to a surface of a roof of a vehicle on a cabin side and having a concave portion concave upward, an opening portion formed at a position facing a rear of the vehicle in the concave portion, and a display device having a display surface disposed in the opening portion with the display surface directed to the rear of the vehicle.

Abstract: The present invention relates to a solid-state image sensor including a pixel array section including a plurality of unit pixels each having a photoelectric conversion unit, the plurality of unit pixels being arranged in a matrix, a sample-and-hold unit configured to sample and hold a pixel signal output from the unit pixel through a vertical signal line provided in association with column arrangement of the pixel array section, and an analog-to-digital conversion unit configured to convert a pixel signal output from the sample-and-hold unit into a digital signal. Then, the sample-and-hold unit has two sample-and-hold circuits in parallel for one vertical signal line, and at least one of the two sample-and-hold circuits has at least two sampling capacitors.

Abstract: A vehicular display device according to an embodiment includes a light shielding housing fixed to a surface of a roof of a vehicle on a cabin side and having a concave portion concave upward, an opening portion formed at a position facing a rear of the vehicle in the concave portion, and a display device having a display surface disposed in the opening portion with the display surface directed to the rear of the vehicle.

Abstract: The present technology is concerned with a solid-state imaging device, a method of driving a solid-state imaging device, and an electronic device which are capable of reducing power supply noise of a pixel signal with a single-ended circuit arrangement. The solid-state imaging device includes a pixel section including a plurality of unit pixels disposed for photoelectric transduction, a power supply noise detector detecting a noise component from a power supply used to energize the unit pixels and outputting a single-ended canceling signal including a canceling component for canceling the noise component, a sample and hold section configured to sample single-ended pixel signals output from the unit pixels and hold and output pixel signals representing the sampled pixel signals from which the noise component has been removed on the basis of the canceling signal, and an A/D converter performing A/D conversion on the pixel signals that have been held.

Abstract: The present technology is concerned with a solid-state imaging device, a method of driving a solid-state imaging device, and an electronic device which are capable of reducing power supply noise of a pixel signal with a single-ended circuit arrangement. The solid-state imaging device includes a pixel section including a plurality of unit pixels disposed for photoelectric transduction, a power supply noise detector detecting a noise component from a power supply used to energize the unit pixels and outputting a single-ended canceling signal including a canceling component for canceling the noise component, a sample and hold section configured to sample single-ended pixel signals output from the unit pixels and hold and output pixel signals representing the sampled pixel signals from which the noise component has been removed on the basis of the canceling signal, and an A/D converter performing A/D conversion on the pixel signals that have been held.

Abstract: A folding circuit and an analog-to-digital converter wherein a response to small signals is improved, a load on a clock signal can be reduced, and the increase of circuit area can be prevented. The circuit includes a reference voltage generating circuit that generates a plurality of differential voltages as reference voltages, and a plurality of amplification circuits that convert differential voltages between the plurality of reference voltages and an analog input voltage to differential currents, and output these differential currents. The output ends of the amplification circuits are alternately connected. Each of the amplification circuit is configured by a differential amplifier circuit having cascode output transistors (145, 146). A switch (144), which is turned on in synchronization with the control clock, is provided between the both sources of the cascode output transistors (145,146).

Abstract: A method is provided for driving a liquid crystal display panel including first and second data line sets each including an even number of arrayed data lines, and a plurality of pixels sharing a common electrode having a constant potential. The method is composed of: time-divisionally selecting data lines from each of the first and second data line sets; and providing data signals on the selected data lines to write the data signals into the pixels therethrough. An order of selecting the data lines from each of the first and second data lines and polarities of the data signals written into the pixels are determined so that polarities of the data signals on the data lines selected from the first data line set are opposite to those of the data lines selected from the second data line set.

Abstract: A folding circuit and an analog-to-digital converter wherein a response to small signals is improved, a load on a clock signal can be reduced, and the increase of circuit area can be prevented. The circuit includes a reference voltage generating circuit that generates a plurality of differential voltages as reference voltages, and a plurality of amplification circuits that convert differential voltages between the plurality of reference voltages and an analog input voltage to differential currents, and output these differential currents. The output ends of the amplification circuits are alternately connected. Each of the amplification circuit is configured by a differential amplifier circuit having cascode output transistors (145, 146). A switch (144), which is turned on in synchronization with the control clock, is provided between the both sources of the cascode output transistors (145,146).

Abstract: A liquid crystal display apparatus is composed of an LCD panel including data lines, and an LCD driver. The LCD driver includes: a positive drive circuit providing a positive data signal having positive polarity with respect to a ground level of the LCD driver for one of the data lines; and a negative drive circuit providing a negative data signal having negative polarity with respect to the ground level of the LCD driver for another one of the data lines.

Abstract: An encode circuit includes a digital average unit that receives cyclic thermometer codes or standard thermometer codes, and that reduces a bubble error in the received thermometer codes by a majority vote rule, a logical boundary detection unit that detects a logical boundary in the thermometer codes output from the digital average unit, and an encoder unit that generates output codes based on output signals from the logical boundary detection unit.

Abstract: In a clock extracting circuit according to the present invention, after serial data is subjected to oversampling using a reference clock of 2N times a frequency of the serial data, clock timing in a period of time in which signal level remains unchanged for a long duration is extracted. Clock timing based on a point of change in the signal level is also extracted, and a final clock timing signal is outputted according to these timings detected. Thus, clock timing can be extracted accurately without omission even when the input signal includes jitter. Further, the clock extraction is performed without converting the input signal into parallel data and by simple processing. A clock extracting circuit for extracting a clock signal from the received serial data with high accuracy is thus realized without increasing the circuit scale.