Abstract: An information apparatus includes at least one memory and at least one processor which function as: a display control unit configured to perform display control of a virtual object so that the virtual object is disposed in a three-dimensional space which becomes a visual field of a user; and a selection unit configured to set the virtual object included in a selection range in the three-dimensional space, which is selected using an operation body at a position of a hand of the user, to a selected state, wherein the selection range is a three-dimensional range determined by expanding a two-dimensional selected region, which the user specifies using the operation body, in the depth direction.

Abstract: The invention relates to a process for preparing a partial glyceride, which includes, in a glycerolysis reaction of oil or fat making use of a lipase, conducting the reaction in the presence of water under conditions that crystals are partially precipitated in the reaction system in the course of the reaction and the concentration of free fatty acids in an oil phase amounts to at least 5% by weight.

Abstract: It is an object of the invention to provide a semiconductor memory device with a reduced access time by devising a layout of a circuit without elaborate modification. A Y address buffer is situated on the side of an address pad array (the right side), and outputs a signal for controlling Y address decoder situated on the right side and a circuit block communicated therewith. The Y address decoders on the right side control the Y addresses of memory cells in the memory cell arrays C and D in case that data are read therefrom or written thereinto. The circuit block communicated with the Y address buffer outputs a signal to the address decoders on the side of a DQ pad array (the left side) in accordance with the signal inputted from the Y address buffer. The Y address decoders on the left side control the Y addresses of the memory cells in the memory cell arrays A and B in accordance with the signal inputted from the circuit block communicated with the Y address buffer.

Abstract: According to one disclosed embodiment, a synchronous semiconductor storage device (100) includes a circuit for accomplishing mode setting operations after a test mode is entered, where the test mode includes a higher frequency internal clock. A synchronous semiconductor storage device (100) generates a first internal synchronous clock signal ICLK which can be used to enter mode setting values to a mode register setting circuit (122). At the same time, an external synchronous signal CSB can be applied to generate a second internal synchronous clock signal CSCLK. The ICLK and CSCLK values can be used to generate a higher frequency clock ICLK′ in a test mode. The ICLK′ signal can be applied to internal circuits (124) allowing such circuits to operate at a higher speed. The ICLK′ signal is not applied to the mode register setting circuit (122), thereby avoiding the possible latching of incorrect mode setting values by the mode register setting circuit (122).

Abstract: A semiconductor memory device includes a plurality of memory cell groups, the data for the plurality of memory cell groups being transmitted through mutually different buses, and a redundancy memory cell group common to the plurality of memory cell groups. The semiconductor memory device further includes a control circuit for transmitting data for one or more memory cells of the redundancy memory cell group in place of data for one or more defective memory cells in any of the plurality of memory cell groups. Each of the plurality of memory cell groups is provided corresponding to every different input/output terminal of the memory device, or the plurality of memory cell groups are provided corresponding to a common input/output terminal of the memory device.

Abstract: In a roll call tester, a redundancy circuit is provided which, upon predetermined normal cell addressing, activates the normal cell while rendering the redundancy cell nonactive, and, upon predetermined redundancy cell addressing, renders the normal cell nonactive while, when the roll call test signal in the test signal activation circuit is nonactive, activating the redundancy cell. This construction can realize a roll call test while eliminating the need to use a redundancy detection circuit and a signal involved in the detection thereof, and can reduce chip area.